Abstract: The present invention relates to a semiconductor device, a unique ID of the semiconductor device and a method for verifying the unique ID. Thus, original data (bit string) having 127-bit length [126:0] is inputted at step S1. Then, it is determined whether the number of bits of “1” in the bit string [126:0] inputted at the step S1 is more than the half of the bits of the bit string (that is, not less than 64) or not at step S2. When the number is not less than 64, the process proceeds to step S3. At the step S3, the bit string [126:0] is inverted and an invert bit [127] is set to “1”. Then, the process proceeds to step S5. At the step S5, the fuse corresponding to the bit string [126:0] and the bit [127] are cut by LT.

Abstract: The present invention relates to a semiconductor device, a unique ID of the semiconductor device and a method for verifying the unique ID. Thus, original data (bit string) having 127-bit length [126:0] is inputted at step S1. Then, it is determined whether the number of bits of “1” in the bit string [126:0] inputted at the step S1 is more than the half of the bits of the bit string (that is, not less than 64) or not at step S2. When the number is not less than 64, the process proceeds to step S3. At the step S3, the bit string [126:0] is inverted and an invert bit [127] is set to “1”. Then, the process proceeds to step S5. At the step S5, the fuse corresponding to the bit string [126:0] and the bit [127] are cut by LT.

Abstract: A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number information indicative of the number of wait cycles for an access by the CPU to that peripheral circuit, and a wait control circuit providing wait control for the access by the CPU to that peripheral circuit based on the number of wait cycles held by the wait control register.

Abstract: A semiconductor device includes a plurality of internal row pads and external row pads, consisting of a pad and a pad-control portion that controls an input signal from and an output signal to the pad. The pad and the pad-control portion of the internal row pad are disposed in relationship of reversed arrangement with the pad and the pad-control portion of the external row pad. A plurality of the internal row pads in which the pad and the pad-control portion are disposed in the bonding direction and a plurality of the external row pads in which the pad and the pad-control portion are disposed in the bonding direction are each alternately disposed adjacent perpendicularly to the bonding direction.

Abstract: A semiconductor device includes a plurality of internal row pads and external row pads, consisting of a pad and a pad-control portion that controls an input signal from and an output signal to the pad. The pad and the pad-control portion of the internal row pad are disposed in relationship of reversed arrangement with the pad and the pad-control portion of the external row pad. A plurality of the internal row pads in which the pad and the pad-control portion are disposed in the bonding direction and a plurality of the external row pads in which the pad and the pad-control portion are disposed in the bonding direction are each alternately disposed adjacent perpendicularly to the bonding direction.

Abstract: A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number information indicative of the number of wait cycles of an access by the CPU to that peripheral circuit, and a wait control circuit which performs a wait control of the access by the CPU to that peripheral circuit based on the information of the number of wait cycles held by the wait control register.

Abstract: A logical synthesizing device and logical synthesizing method capable of generating a net list from a feedback loop added flip-flop excellent in layout efficiency. In a cell library, cells of feedback loop added flip-flop are newly registered together with existing various cells. The feedback loop portion of this feedback loop added flip-flop is formed in an optimum layout composition in consideration of the setup time and hold time. A logical synthesizing section, using the cells registered in the cell library, generates a net list for realizing a logical function description, and outputs to a test design section At this time, the feedback loop forming portion in the input and output of the flip-flop generates the net list by using the feedback loop added flip-flop.