Abstract: A synchronous detector used in a code division multiple access (CDMA) communication receiver comprises a correlator and a pre-synchronous decision circuit. The correlator calculates a plurality of correlation values between a received signal spread with an x-chip sequence of a spread code and n-chip correlation coefficients for different phase timings. The pre-synchronous decision circuit, coupled to the correlator, generates at least one timing control signal indicating a phase timing corresponding to a highest correlation value. The correlator comprises a synchronous estimator that estimates a synchronous phase by calculating the correlation values between the received signal and the n-chip correlation coefficients every cycle of the spread code and by accumulating the correlation values. The synchronous estimator comprises an n-chip correlation coefficient generator that generates the n-chip correlation coefficients at phase timings indicated by a timing control signal.

Abstract: A viterbi decoder includes a branch metric calculation unit, a path selection unit, and a path memory unit. The branch metric calculation unit calculates a likelihood of a branch obtained through a received convolutional code. The path selection unit adds metrics of branches extending from a time point t=n to a time point t=n+1 obtained at the branch metric calculation unit to path metrics of a number of states that a convolutional code may assume at the time point t=n and compares path metrics for each state at the time point t=n+1 to select an optimal path for each state at the time point t=n+1. The path memory unit stores in memory path data corresponding to the optimal path for each state at individual points in time.