Patents by Inventor Yasufumi Tokura

Yasufumi Tokura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4906418
    Abstract: A method for teaching a machining line to be machined is disclosed. A borderline is formed along the machining line on a workpiece. Then, a borderline sensor is moved across the borderline at each sensing position. The positions of the sensor are stored as a teaching position at each time when the borderline is detected by the sensor. The sensing interval between each teaching position is automatically adjusted according to the change in the curvature of the borderline. At the place where the curvature of the borderline becomes large, the sensing interval is shortened in order to maintain teaching accuracy.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: March 6, 1990
    Assignee: Toyoda-Koki Kabushiki-Kaisha
    Inventors: Yasufumi Tokura, Shigeo Hotta, Osamu Matsuda, Hajime Fukami
  • Patent number: 4266375
    Abstract: A feed control apparatus wherein a servomotor control device responsive to feed pulses distributed from a numerical controller controls a d.c. servomotor to advance a grinding wheel carriage of a grinding machine through the rotation of a feed screw successsively at a speed-up feed rate, a rapid feed rate, a slow-down feed rate and a grinding feed rate. A detection device is provided, which outputs a velocity checking signal to an abnormality confirmation device when the carriage reaches a velocity checking point defined within a slow-down feed range. When confirming that the feed rate of the carriage has exceeded a reference feed rate lower than the rapid feed rate, the abnormality confirmation device applies a stop signal to an emergency stop control circuit in response to the velocity checking signal, so that the rotation of the servomotor is immediately discontinued.
    Type: Grant
    Filed: March 7, 1980
    Date of Patent: May 12, 1981
    Assignee: Toyoda-Koki Kabushiki-Kaisha
    Inventors: Hideo Nishimura, Yasufumi Tokura, Kunihiko Unno, Minoru Enomoto, Isamu Yokoe, Norihiko Shimizu, Haruo Ohmura
  • Patent number: 4025902
    Abstract: A general purpose sequence controller wherein a schematic electric circuit diagram comprising a ladder network of circuit lines disposed between two vertical bus lines is changeable and simulated by a special purpose control program. A logic operation circuit comprises first and second circuit means for examining an external input signal in accordance with examine commands of logical AND and OR functions, respectively, first and second memory means for temporarily memorizing the examined results of the first and second circuit means, respectively, third memory means for temporarily memorizing the application of the examine command of the logical OR function, and identifying circuit means for identifying the examined results of the logic operations in accordance with the contents of the first, second and third memory means.
    Type: Grant
    Filed: June 13, 1974
    Date of Patent: May 24, 1977
    Assignee: Toyoda Koki Kabushiki Kaisha
    Inventors: Hisaji Nakao, Katutoshi Naruse, Kazuhiko Hasegawa, Sadao Kawade, Yasufumi Tokura, Kazuo Matsuno
  • Patent number: 4019175
    Abstract: A programmable sequence controller is disclosed which includes a controller memory having at least one read-only memory unit for storing a sequence program comprising a series of instructions each including an operation code and address information. An operation control device is also provided for examining an external input in accordance with an appropriate instruction. An input network permits application of external inputs designated by the address information to the operation control device, and an output network is provided for transmitting a control signal based on the examination result from the operation control device. A program input network including a read-write memory is provided for storing a part of the sequence program, which part is loadable in one read-only memory unit.
    Type: Grant
    Filed: April 15, 1975
    Date of Patent: April 19, 1977
    Assignees: Toyoda Koki Kabushiki Kaisha, Toyota Jidosha Kogyo Kabushiki Kaisha
    Inventors: Hisaji Nakao, Yasufumi Tokura, Kazuo Matsuno, Toshihiko Yomogida
  • Patent number: 3996565
    Abstract: A sequence controller comprising a logic operation circuit for examining an external input with an examine command in accordance with a program. The logic operation circuit comprises block means for discontinuing a next examination of a logical function of a group of logical functions in response to a preceeding examination result of a logical function to thereby execute a logic operation non-sequentially.
    Type: Grant
    Filed: July 3, 1974
    Date of Patent: December 7, 1976
    Assignees: Toyoda Koki Kabushiki Kaisha, Toyoda Jidosha Kogyo Kabushiki Kaisha
    Inventors: Hisaji Nakao, Yasufumi Tokura, Toshihiko Yomogida, Kazuo Matsuura