Patents by Inventor Yasufumi Uchida

Yasufumi Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8288715
    Abstract: An oxygen detection method, includes: preparing a grid, an ion collector, and a filament in which an oxide are formed on a surface of metal; controlling a filament current flowing to the filament so that an emission current becomes constant; discharging thermionic electrons which are caused by heat generation by applying the filament current, and generating ions by ionizing a gas; capturing the ions with the ion collector; and detecting oxygen being present in a vacuum processing chamber by measuring a filament current value.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 16, 2012
    Assignee: Ulvac, Inc.
    Inventors: Toyoaki Nakajima, Takeshi Miyashita, Yasushi Nagata, Yasufumi Uchida, Hideki Yoshizawa
  • Publication number: 20110315872
    Abstract: An oxygen detection method, includes: preparing a grid, an ion collector, and a filament in which an oxide are formed on a surface of metal; controlling a filament current flowing to the filament so that an emission current becomes constant; discharging thermionic electrons which are caused by heat generation by applying the filament current, and generating ions by ionizing a gas; capturing the ions with the ion collector; and detecting oxygen being present in a vacuum processing chamber by measuring a filament current value.
    Type: Application
    Filed: March 16, 2010
    Publication date: December 29, 2011
    Applicant: ULVAC, INC.
    Inventors: Toyoaki Nakajima, Takeshi Miyashita, Yasushi Nagata, Yasufumi Uchida, Hideki Yoshizawa
  • Patent number: 8044518
    Abstract: A second semiconductor chip and a junction member are mounted on a first semiconductor chip formed with a plurality of first pads on a surface thereof. A resin encapsulating body is provided which seals the first semiconductor chip, the second semiconductor chip and the junction member. The second semiconductor chip includes a plurality of second pads arranged in a central part thereof. The junction member includes first junction pads, second junction pads and connecting portions which connect the first junction pads and the second junction pads respectively. Electrical connections of the second semiconductor chip from the second pads include connections to connecting terminals and connections to the connecting terminals or the first semiconductor chip from the second junction pads via the first junction pads.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: October 25, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yasufumi Uchida
  • Publication number: 20090031563
    Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.
    Type: Application
    Filed: May 20, 2008
    Publication date: February 5, 2009
    Inventors: Yasufumi Uchida, Yoshihiro Saeki
  • Patent number: 7435626
    Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: October 14, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasufumi Uchida, Yoshihiro Saeki
  • Patent number: 7317244
    Abstract: In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: January 8, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasufumi Uchida, Yoshimi Egawa
  • Publication number: 20050161792
    Abstract: A second semiconductor chip and a junction member are mounted on a first semiconductor chip formed with a plurality of first pads on a surface thereof. A resin encapsulating body is provided which seals the first semiconductor chip, the second semiconductor chip and the junction member. The second semiconductor chip includes a plurality of second pads arranged in a central part thereof. The junction member includes first junction pads, second junction pads and connecting portions which connect the first junction pads and the second junction pads respectively. Electrical connections of the second semiconductor chip from the second pads include connections to connecting terminals and connections to the connecting terminals or the first semiconductor chip from the second junction pads via the first junction pads.
    Type: Application
    Filed: October 8, 2004
    Publication date: July 28, 2005
    Inventor: Yasufumi Uchida
  • Publication number: 20040232539
    Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.
    Type: Application
    Filed: June 15, 2004
    Publication date: November 25, 2004
    Inventors: Yasufumi Uchida, Yoshihiro Saeki
  • Patent number: 6812556
    Abstract: A semiconductor device including a package body, a substrate contained within the package body and having a first side and an opposite second side, a first chip mounted on the first side of the substrate and within the package body, a second chip mounted on the second side of the substrate and within the package body and a plurality of leads each including an inner lead portion contained within the package body and an outer lead portion located outside the package body wherein each inner lead portion includes first and second bends to define a step configuration and wherein a distal end of each inner lead portion is mounted to the second side of the substrate.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: November 2, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasufumi Uchida
  • Patent number: 6787915
    Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: September 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasufumi Uchida, Yoshihiro Saeki
  • Patent number: 6690089
    Abstract: A semiconductor device includes a first semiconductor element provided with bonding electrodes at a predetermined pitch and lead frames provided on the first semiconductor element which work as electrical inputs/outputs. The semiconductor device further includes a substrate provided on the lead frames that is provided with metal wirings having a predetermined pitch, and a second semiconductor element provided on the substrate and provided with bonding electrodes having substantially the same pitch as the metal wirings. The semiconductor device further includes solder balls for respectively electrically connecting the bonding electrodes provided on the second semiconductor element and the metal wirings formed on the substrate, first metal wires for respectively electrically connecting the bonding electrodes provided on the first semiconductor element and the lead frames, and second metal wires for respectively electrically connecting the metal wirings provided on the substrate and the lead frames.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: February 10, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasufumi Uchida
  • Patent number: 6686223
    Abstract: A semiconductor device includes a substrate (101); a first semiconductor chip (102) mounted on the substrate; and a first insulating layer (105) which is provided on the first semiconductor chip. The device further includes a metal layer (102) which is provided on the first insulating layer; a second insulating layer (117) which is provided on the metal layer; and a second semiconductor chip (104) which is provided on the second insulating layer.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: February 3, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Yasufumi Uchida
  • Publication number: 20030214023
    Abstract: A semiconductor device includes a first semiconductor chip formed with bonding electrodes in predetermined widths and lead frames provided on the first semiconductor element and working as electrical inputs/outputs. The semiconductor device further includes a substrate provided on the lead frames and formed with metal wirings each having a predetermined width, and a second semiconductor chip provided on the substrate and formed with bonding electrodes having substantially the same width as the metal wirings. The semiconductor device further includes solder balls for respectively electrically connecting the bonding electrodes formed on the second semiconductor element and the metal wirings formed on the substrate, first metal wires for respectively electrically connecting the bonding electrodes formed on the first semiconductor element and the lead frames, and second metal wires for-respectively electrically connecting the metal wirings formed on the substrate and the lead frames.
    Type: Application
    Filed: September 5, 2002
    Publication date: November 20, 2003
    Inventor: Yasufumi Uchida
  • Publication number: 20030211656
    Abstract: A semiconductor device includes a substrate (101); a first semiconductor chip (102) mounted on the substrate; and a first insulating layer (105) which is provided on the first semiconductor chip. The device further includes a metal layer (102) which is provided on the first insulating layer; a second insulating layer (117) which is provided on the metal layer; and a second semiconductor chip (104) which is provided on the second insulating layer.
    Type: Application
    Filed: April 14, 2003
    Publication date: November 13, 2003
    Inventor: Yasufumi Uchida
  • Publication number: 20030189258
    Abstract: A semiconductor device including a package body, a substrate contained within the package body and having a first side and an opposite second side, a first chip mounted on the first side of the substrate and within the package body, a second chip mounted on the second side of the substrate and within the package body and a plurality of leads each including an inner lead portion contained within the package body and an outer lead portion located outside the package body wherein each inner lead portion includes first and second bends to define a step configuration and wherein a distal end of each inner lead portion is mounted to the second side of the substrate.
    Type: Application
    Filed: March 21, 2003
    Publication date: October 9, 2003
    Inventor: Yasufumi Uchida
  • Patent number: 6620649
    Abstract: In a method of fabricating a semiconductor device, a semiconductor wafer is provided with a plurality of semiconductor elements formed thereon. An insulating adhesive is selectively provided over respective predetermined areas of the semiconductor elements. The semiconductor wafer is then separated into the semiconductor elements, each having corresponding portions of the insulating adhesive thereon.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: September 16, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasufumi Uchida
  • Patent number: 6614112
    Abstract: A semiconductor device includes a substrate; a metal layer formed on the substrate; an insulating layer, which is formed on the metal layer and is provided with a via-hole through it; and a bonding pad formed above the via-hole. The bonding pad comprises an inner portion arranged in the via-hole and an outer portion arranged above the via-hole. The boding pad is made of a conductive resin having a shock absorbing characteristic.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 2, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasufumi Uchida
  • Publication number: 20030132516
    Abstract: In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 17, 2003
    Inventors: Yasufumi Uchida, Yoshimi Egawa
  • Patent number: 6576997
    Abstract: A semiconductor device includes a substrate (101); a first semiconductor chip (102) mounted on the substrate; and a first insulating layer (105) which is provided on the first semiconductor chip. The device further includes a metal layer (102) which is provided on the first insulating layer; a second insulating layer (117) which is provided on the metal layer; and a second semiconductor chip (104) which is provided on the second insulating layer.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: June 10, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Yasufumi Uchida
  • Patent number: 6569755
    Abstract: According to a typical invention of the inventions disclosed in the present application, a semiconductor chip with an electronic circuit formed therein is fixed to a die pad for a lead frame having projections formed on the back thereof, with an organic dies bonding agent. Pads on the semiconductor chip, and inner leads are respectively electrically connected to one another by metal thin lines. These portions are sealed with a molding resin. Further, each inner lead extends to the outside of the molding resin and is processed into gull-wing form for substrate mounting. Moreover, the inner lead is processed by soldering so that an external terminal is formed. Thus, since the projections are provided on the back of the die pad, the back of a packing material is brought into point contact with that of the die pad as compared with the conventional face-to-face contact. It is therefore possible to minimize the transfer of organic substances from the packing material.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: May 27, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shigeru Yamada, Yasufumi Uchida, Noriko Murakami, Yoshinori Shizuno