Patents by Inventor Yasufumi Yoshizawa

Yasufumi Yoshizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5619691
    Abstract: A file sharing method and system for a multiprocessor system has an auxiliary storage unit that is shared in use by a plurality of processors each adopting virtual storage management. An auxiliary page table for storing on a page-by-page basis addresses of files contained in the auxiliary storage unit is prepared on a main storage provided for each of the processors. In response to a file map request issued by a program, an address of the file stored in said auxiliary storage unit is stored in the auxiliary page file. When the file is not stored in the main storage, a page exception interruption occurs, in response to which the address of the file stored in the auxiliary page table is referenced to for thereby transferring the file to the main storage from the auxiliary storage unit. The file stored in the auxiliary storage unit is transferred in the state undergoing an exclusion control.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: April 8, 1997
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Hisashi Katada, Toshiaki Arai, Yasufumi Yoshizawa, Yoshitaka Ohfusa, Masayuki Kami
  • Patent number: 5193172
    Abstract: An information processing system managing a virtual memory by using a real memory system comprising a single or a plurality of processors which, when a real page allocation request occurs in a processor or task keeping the use priority that the real pages of a group among the divided groups of the real pages of said memory can be used in a priority basis, allocated the real pages belonging to said group for which said processor or task keeps the use priority to said processor or task in a priority basis so as to decrease the cache cancel rate and the mapping fault occurrence rate and to allow for smoothing and high speed access of the main memory.
    Type: Grant
    Filed: January 22, 1990
    Date of Patent: March 9, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Arai, Yoshitaka Ohfusa, Hirohumi Nagasuka, Yasufumi Yoshizawa
  • Patent number: 4991082
    Abstract: An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area boundary, a page table is prepared for each virtual address space. Thus, virtual pages which are not used as the system common area in the bondary segment can be used by jobs as job private areas.The real page is fixedly allocated to the virtual page belonging to the system common area in the boundary segment. Thus, it is not necessary to simultaneously update page tables for the system common area. Those virtual pages may be subjects of dynamic allocation of the virtual storage.
    Type: Grant
    Filed: October 28, 1986
    Date of Patent: February 5, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Yasufumi Yoshizawa, Taketoshi Sakuraba, Toshiaki Arai, Toshiyuki Kinoshita, Minoru Shibamiya, Takashige Kubo
  • Patent number: 4903234
    Abstract: In a memory system having a storage device and a key storage keeping key data controlling an access to the storage device, there is disposed a key address translation structure for obtaining an address of an entry of the key storage based on an address of the storage device to which an access request is issued. As a result, when subdividing the storage device according to the key data setting unit, each subdivided area can be assigned with a variable size and a plurality of sizes are enabled to be specified for the key data setting units at the same time.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: February 20, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Taketoshi Sakuraba, Hisashi Katada, Yoshitaka Ohfusa, Yasufumi Yoshizawa, Toshiaki Arai, Hiroo Miyadera
  • Patent number: 4703422
    Abstract: In a memory hierarchy system having two or more hierarchy storages of different access speeds and programs and/or data to be loaded on the hierarchy storages, an activity information acquisition unit and a display unit are provided to present information regarding selection of programs and/or data to be loaded on a higher level in memory hierarchy, a unit is provided which automatically decides loading of the programs and/or data on the higher level and executes reallocation of the programs and/or data on the basis of the information, and a unit is provided which permits the user to change the loading by using a user command. The user can make full use of these units during execution of the memory hierarchy control. In an embodiment, priority for the programs and/or data to be loaded on the higher level is calculated and decided. The programs and/or data are written into the real storage in accordance with their priority to increase the real storage hit rate upon occurrence of a next request for loading.
    Type: Grant
    Filed: December 28, 1984
    Date of Patent: October 27, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Kinoshita, Toshiaki Arai, Takao Sato, Takashige Kubo, Yasufumi Yoshizawa, Hiromichi Mori