Abstract: A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.

Abstract: In a Video processor, an analog composite video signal is converted by an A/D converter (10) to a digital bit sequence in response to a system clock pulse. By using the system clock pulse and horizontal and vertical synchronizing pulses separated from the composite signal, a horizontal blanking interval and a vertical blanking interval are detected by control circuitry (21.about.24) and the read/write operations of a field memory (12) are disabled during the horizontal and vertical blanking intervals and enabled at other times. The picture information from the memory is converted by a D/A converter (13) to analog form in response to the system clock pulse. A multiplex of a digital pedestal level signal and a digital synchronization level signal is supplied to the D/A converter (13) when the memory is disabled.

Abstract: The semiconductor memory device according to the present invention includes a plurality of memory cells that are provided in array form and a plurality of bit lines and word lines that are respectively connected to these memory cells, and comprises a memory cell array arranged so as to form pairs of bit lines, a data register circuit consisting of a plurality of registers, and selection means for respectively connecting predetermined bit line pairs out of the plurality of bit line pairs to a plurality of registers in response to a control signal.This data register circuit is formed by arranging the plurality of registers in a single line.With such a constitution, the number of registers that constitute the data register circuit can be reduced compared with the conventional device.

Abstract: A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.

Abstract: A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs and word lines, a sense amplifier connected to each member of the bit line pair, a transfer gate provided between one end of the bit line and the sense amplifier, and a potential supply circuit connected respectively to the bit line pairs between the sense amplifiers.

Abstract: A semiconductor memory device comprises a plurality of memory cells respectively storing data bits in a rewritable manner, a plurality of digit lines coupled to the memory cells, a column selector unit having a plurality of transfer gate transistors coupled between the digit lines and a data line, and a read/write controlling unit responsive to address bits and allowing one of the transfer gate transistors to couple the data line to the associated digit line, wherein the read/write controlling unit is further responsive to a bit pattern stored in a register and allows a plurality of transfer gate transistors to couple the data line to the associated digit lines so that a new data bit is concurrently written into a plurality of memory cells.

Abstract: A semiconductor memory device comprises a random memory cell array halved into first and second memory areas, and a data register coupled to digit lines of the random memory cell array in parallel for temporarily holding data read out onto the respective digit lines from selected memory cells. A row address generator receives an input row address and generates a first row address signal designating a first row corresponding to the input row address, and a second row address designating a second row different from the first row.