Abstract: In a semiconductor device comprising: a wiring board comprising a conductor wiring having a predetermined pattern provided on the surface of an insulating substrate; an elastomer provided on the wiring board; a semiconductor chip bonded onto the wiring board through the elastomer; and an insulator for sealing the periphery of the semiconductor chip and the elastomer, the semiconductor chip in its external terminal being electrically connected to the conductor wiring, a part of the elastomer is exposed onto the surface of the insulator. By virtue of the above construction, a lowering in device reliability can be prevented.

Abstract: A structure of a semiconductor device of a chip scale package structure is provided. In the semiconductor device, the limitation to size reduction due to the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this compatibility among packages can be kept.

Abstract: In a semiconductor device comprising: a wiring board comprising a conductor wiring having a predetermined pattern provided on the surface of an insulating substrate; an elastomer provided on the wiring board; a semiconductor chip bonded onto the wiring board through the elastomer; and an insulator for sealing the periphery of the semiconductor chip and the elastomer, the semiconductor chip in its external terminal being electrically connected to the conductor wiring, a part of the elastomer is exposed onto the surface of the insulator. By virtue of the above construction, a lowering in device reliability can be prevented.

Abstract: A semiconductor chip is mounted on a tape carrier by interposing an elastmer layer therebetween, so that thermal stress caused by a difference of thermal expansion coefficients of the semiconductor chip and the tape carrier is relieved. The tape carrier is structured by an insulating film and a plurality of leads formed on the insulating film. The insulating film has an opening for bonding the plurality of leads to the electrodes of the semiconductor chip, and the elastmer layer comprises first and second elastmer layers provided on the opposite sides of the opening to be separated around at least one end of the opening. The opening may be divided into a plurality of openings, in each of which a corresponding one or some of connected portions of the plurality of leads and the electrodes of the semiconductor chip are positioned, and sealing resins are filled in the plurality of openings to seal the connected portions.

Abstract: “”-shaped slits and linking portions are previously provided so as to surround a semiconductor chip-mounting region in a TAB tape. A semiconductor chip is applied onto the semiconductor chip-mounting region. The semiconductor chip in its electrode pad is connected by bonding to the TAB tape in its inner lead. The bonded connection is subjected to plastic molding. Solder balls are provided on the backside of the TAB tape in its portion corresponding to the semiconductor chip-mounting portion. Thereafter, the package portion is cut off at the cutting position in the linking portion of the slits. By virtue of the above constitution, highly reliable BGA type semiconductor devices can be produced while reducing the thickness and reducing the size.

Abstract: “”-shaped slits and linking portions are previously provided so as to surround a semiconductor chip-mounting region in a TAB tape. A semiconductor chip is applied onto the semiconductor chip-mounting region. The semiconductor chip in its electrode pad is connected by bonding to the TAB tape in its inner lead. The bonded connection is subjected to plastic molding. Solder balls are provided on the backside of the TAB tape in its portion corresponding to the semiconductor chip-mounting portion. Thereafter, the package portion is cut off at the cutting position in the linking portion of the slits. By virtue of the above constitution, highly reliable BGA type semiconductor devices can be produced while reducing the thickness and reducing the size.

Abstract: A structure of a semiconductor device of a CSP structure is provided. In the semiconductor device, the limitation by the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this, compatibility among packages can be kept.

Abstract: A tape carrier is constituted comprising land 12 for solder ball, formed in a predetermined pattern on insulating film 7 having device hole 10 formed in the middle, leads 9 to be connected to a semiconductor chip, plating power-feeding lead 13 having one end connected to lead 9 and formed on insulating film 7, and easily-broken part 19 provided in the middle of the power-feeding leads. A semiconductor device is constituted wherein tape carrier 2 is provided with plating power-feeding lead 13 formed on insulating film 7, one end of which is drawn out of insulating film 7, the other end being connected to leads 9, and plating power-feeding lead 13 is disconnected from the leads when semiconductor chip 1 is installed. Thus, a tape carrier for BGA which is manufactured easily, capable of achieving higher density of wiring in the wiring pattern, improved in water-resistance and reliability, and a semiconductor device using the same are provided.

Abstract: A method of manufacturing a double-sided circuit tape carrier comprising an insulating film like a polyimide tape, circuit wiring patterns on both sides thereof, and via holes through which at least a part of the circuit wiring patterns on both sides are electrically connected with each other. A copper thin film is patterned by photoetching. Via holes are formed through the insulating film by irradiating a laser beam by using the patterned copper thin film as a mask. Then, a conductive layer of a graphite conductive thin film and a copper plating layer is formed. The copper thin film is patterned by photoetching forming a chip hole and an outer lead hole through the insulating film by irradiating a laser beam. Finally, one of the copper thin films is patterned by photoetching to form circuit wiring pattern.