Patents by Inventor Yasuharu Kawai

Yasuharu Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982961
    Abstract: A fixing device includes an endless belt, a rotatable pressing member, a pad member inside of the belt, and a sliding member held by the pad member and sliding on an inner circumferential surface of the belt in a nip. The rotatable pressing member nips and feeds a recording material in the nip in cooperation with the belt and fixes a toner image on the recording material by applying heat and pressure. The sliding member includes a base material layer on which a plurality of projections projecting toward the rotatable pressing member are formed on a side sliding with the belt and a sliding layer provided on an outer surface of the plurality of projections. A shape of a surface of the sliding layer is a curved surface and a radius of curvature R of the curved surface satisfies 300 ?m?R?850 ?m.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: May 14, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Kawai, Yasuharu Toratani, Hiroshi Miyamoto, Akiyoshi Shinagawa, Ayano Ogata, Daigo Matsuura, Misa Kawashima, Masanobu Tanaka, Asuna Fukamachi
  • Patent number: 11960224
    Abstract: A fixing device includes an endless belt, a rotatable pressing member, a pad member inside of the belt, and a sliding member held by the pad member and sliding on an inner circumferential surface of the belt in a nip. The rotatable pressing member nips and feeds a recording material in the nip in cooperation with the belt and fixes a toner image on the recording material by applying heat and pressure. The sliding member includes a base material layer on which a plurality of projections projecting toward the rotatable pressing member are formed on a side sliding with the belt and a sliding layer provided on an outer surface of the plurality of projections. A leading end of the plurality of projections is a plane and an average roughness (Ra) of the plane satisfies 0.13 ?m?Ra?1.67 ?m.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 16, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Akiyoshi Shinagawa, Yasuharu Toratani, Hiroshi Miyamoto, Daigo Matsuura, Hiroki Kawai, Ayano Ogata, Masanobu Tanaka, Asuna Fukamachi, Misa Kawashima
  • Patent number: 6995429
    Abstract: A semiconductor device in accordance with the present invention is equipped with a gate electrode 10 formed on a BOX layer 2, a gate oxide film 11 formed on the gate electrode, a body region 12a composed of epitaxial Si formed on the gate oxide film, diffusion layers 18 and 19 for source/drain regions formed on both sides of the body region, and a body terminal connected to the body region for applying a specified potential to the body region. As a result, the substrate floating effect is suppressed even in a transistor having a short gate length and a long gate width.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: February 7, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Yasuharu Kawai
  • Publication number: 20040222447
    Abstract: A semiconductor device in accordance with the present invention is equipped with a gate electrode 10 formed on a BOX layer 2, a gate oxide film 11 formed on the gate electrode, a body region 12a composed of epitaxial Si formed on the gate oxide film, diffusion layers 18 and 19 for source/drain regions formed on both sides of the body region, and a body terminal connected to the body region for applying a specified potential to the body region. As a result, the substrate floating effect is suppressed even in a transistor having a short gate length and a long gate width.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Inventor: Yasuharu Kawai
  • Patent number: 6767776
    Abstract: A semiconductor device in accordance with the present invention is equipped with a gate electrode 10 formed on a BOX layer 2, a gate oxide film 11 formed on the gate electrode, a body region 12a composed of epitaxial Si formed on the gate oxide film, diffusion layers 18 and 19 for source/drain regions formed on both sides of the body region, and a body terminal connected to the body region for applying a specified potential to the body region. As a result, the substrate floating effect is suppressed even in a transistor having a short gate length and a long gate width.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 27, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Yasuharu Kawai
  • Publication number: 20030034528
    Abstract: A semiconductor device in accordance with the present invention is equipped with a gate electrode 10 formed on a BOX layer 2, a gate oxide film 11 formed on the gate electrode, a body region 12a composed of epitaxial Si formed on the gate oxide film, diffusion layers 18 and 19 for source/drain regions formed on both sides of the body region, and a body terminal connected to the body region for applying a specified potential to the body region. As a result, the substrate floating effect is suppressed even in a transistor having a short gate length and a long gate width.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 20, 2003
    Inventor: Yasuharu Kawai