Patents by Inventor Yasuharu Kinoshita
Yasuharu Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763017Abstract: An object of the present disclosure is to provide a metal plate resistor that is capable of reducing a resistance value and a TCR. A metal plate resistor according to the present disclosure includes: a resistor body that includes a metal plate having an upper surface and a lower surface that are spaced apart from each other in a thickness direction; a pair of electrodes that include a metal having a low electrical resistivity and a high TCR in comparison with this resistor body, the pair of electrodes being formed in both ends of the lower surface of the resistor body; and an internal electrode that is formed on the upper surface of the resistor body. The internal electrode includes a metal having a low electrical resistivity in comparison with the resistor body.Type: GrantFiled: May 8, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Yasuharu Kinoshita
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Patent number: 10622122Abstract: An object of the present disclosure is to provide a chip resistor capable of suppressing degradation of long-term reliability, and a method for producing the chip resistor. The chip resistor of the present disclosure includes resistance member formed of metal, and a pair of electrodes respectively formed on both ends of first main surface of resistance member. The chip resistor further includes first protective film formed on second main surface located on a rear side of first main surface of resistance member, second protective film formed on first main surface of resistance member and between the pair of electrodes, and a third protective film formed on a side surface parallel to a direction of a current flowing between the pair of electrodes of resistance member. The side surface of resistance member is provided with a protrusion that protrudes outward when viewed along the current flowing direction.Type: GrantFiled: November 30, 2017Date of Patent: April 14, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yasuharu Kinoshita, Takaaki Tamura
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Publication number: 20200075200Abstract: An object of the present disclosure is to provide a metal plate resistor that is capable of reducing a resistance value and a TCR. A metal plate resistor according to the present disclosure includes: a resistor body that includes a metal plate having an upper surface and a lower surface that are spaced apart from each other in a thickness direction; a pair of electrodes that include a metal having a low electrical resistivity and a high TCR in comparison with this resistor body, the pair of electrodes being formed in both ends of the lower surface of the resistor body; and an internal electrode that is formed on the upper surface of the resistor body. The internal electrode includes a metal having a low electrical resistivity in comparison with the resistor body.Type: ApplicationFiled: May 8, 2018Publication date: March 5, 2020Inventor: YASUHARU KINOSHITA
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Publication number: 20200051716Abstract: An object of the present disclosure is to provide a chip resistor capable of suppressing degradation of long-term reliability, and a method for producing the chip resistor. The chip resistor of the present disclosure includes resistance member (11) formed of metal, and a pair of electrodes (12) respectively formed on both ends of first main surface (11a) of resistance member (11). The chip resistor further includes first protective film (13) formed on second main surface (11b) located on a rear side of first main surface (11a) of resistance member (11), second protective film (14) formed on first main surface (11a) of resistance member (11) and between the pair of electrodes (12), and a third protective film formed on a side surface parallel to a direction of a current flowing between the pair of electrodes (12) of resistance member (11). The side surface of resistance member (11) is provided with a protrusion that protrudes outward when viewed along the current flowing direction.Type: ApplicationFiled: November 30, 2017Publication date: February 13, 2020Inventors: YASUHARU KINOSHITA, TAKAAKI TAMURA
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Patent number: 10340063Abstract: A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.Type: GrantFiled: April 26, 2017Date of Patent: July 2, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yasuharu Kinoshita, Shoji Hoshitoku, Hironori Tsubota, Yasuhiro Kashima
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Publication number: 20180096759Abstract: A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.Type: ApplicationFiled: April 26, 2017Publication date: April 5, 2018Inventors: YASUHARU KINOSHITA, SHOJI HOSHITOKU, HIRONORI TSUBOTA, YASUHIRO KASHIMA
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Patent number: 7772961Abstract: A chip-shaped electronic part includes: a substrate; a pair of upper surface electrodes formed on an upper surface of the substrate; a functional element formed to be electrically connected to the upper surface electrode pair; a pair of lower surface electrodes formed on a lower surface of the substrate at positions opposing the upper surface electrode pair; a pair of end surface electrodes formed on end surfaces of the substrate so that each of the end surface electrode pair is electrically connected to one of the upper surface electrode pair, and to one of the lower surface electrode pair corresponding to the one upper surface electrode; a protective film formed in such a manner as to cover at least the functional element; and a plated layer formed in such a manner as to cover at least each of the upper surface electrode pair, wherein the protective film or the plated layer has at least two points of application at which a load from above the substrate is exerted.Type: GrantFiled: September 9, 2005Date of Patent: August 10, 2010Assignee: Panasonic CorporationInventors: Yasuharu Kinoshita, Toshiki Matsukawa, Naoki Shibuya, Shoji Hoshitoku
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Publication number: 20080094169Abstract: A chip-shaped electronic part includes: a substrate; a pair of upper surface electrodes formed on an upper surface of the substrate; a functional element formed to be electrically connected to the upper surface electrode pair; a pair of lower surface electrodes formed on a lower surface of the substrate at positions opposing the upper surface electrode pair; a pair of end surface electrodes formed on end surfaces of the substrate so that each of the end surface electrode pair is electrically connected to one of the upper surface electrode pair, and to one of the lower surface electrode pair corresponding to the one upper surface electrode; a protective film formed in such a manner as to cover at least the functional element; and a plated layer formed in such a manner as to cover at least each of the upper surface electrode pair, wherein the protective film or the plated layer has at least two points of application at which a load from above the substrate is exerted.Type: ApplicationFiled: September 9, 2005Publication date: April 24, 2008Inventors: Yasuharu Kinoshita, Toshiki Matsukawa, Naoki Shibuya, Shoji Hoshitoku
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Patent number: 7237324Abstract: A multiple chip resistor is manufactured in the following method. First electrode layers are formed on a first surface of a substrate. Resistor elements electrically connected to the first electrode layers, respectively, are formed on the first surface of the substrate. Slits are formed in the substrate for separating the first electrode layers. Edge electrodes connected to the first electrode layers at the edges of the slits, respectively, are formed on respective edges at the slits of the substrate. The substrate is divided at the slits into strip substrates. Portions of the edge electrodes are removed for electrically isolating the resistor elements from each other. The method provides the edge electrodes on each strip substrate with an improved dimensional accuracy, hence allowing the edge electrodes to be isolated electrically from each other. Consequently, the multiple chip resistor is prevented from being mounted defectively when the resistor is surface-mounted.Type: GrantFiled: January 14, 2003Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiki Matsukawa, Yasuharu Kinoshita, Shoji Hoshitoku, Masaharu Takahashi, Yoshinori Ando
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Publication number: 20040113750Abstract: A multiple chip resistor is manufactured in the following method. First electrode layers are formed on a first surface of a substrate. Resistor elements electrically connected to the first electrode layers, respectively, are formed on the first surface of the substrate. Slits are formed in the substrate for separating the first electrode layers. Edge electrodes connected to the first electrode layers at the edges of the slits, respectively, are formed on respective edges at the slits of the substrate. The substrate is divided at the slits into strip substrates. Portions of the edge electrodes are removed for electrically isolating the resistor elements from each other. The method provides the edge electrodes on each strip substrate with an improved dimensional accuracy, hence allowing the edge electrodes to be isolated electrically from each other. Consequently, the multiple chip resistor is prevented from being mounted defectively when the resistor is surface-mounted.Type: ApplicationFiled: October 9, 2003Publication date: June 17, 2004Inventors: Toshiki Matsukawa, Yasuharu Kinoshita, Shoji Hoshitoku, Masaharu Takashi, Yoshinori Ando
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Patent number: 6563214Abstract: An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion adjacent to the groove; and a circuit element formed between the electrodes. An electrode is also formed on the opposing side faces of said substrate at a portion other than the grooves. This structure enables to improve the reliability of a soldered portion even for small electronic components with about 10 &mgr;m thick electrodes such as chip resistors, chip capacitors, and chip inductors.Type: GrantFiled: July 27, 2001Date of Patent: May 13, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Yamada, Takeshi Iseki, Yasuharu Kinoshita
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Publication number: 20020076536Abstract: An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion adjacent to the groove; and a circuit element formed between the electrodes. An electrode is also formed on the opposing side faces of said substrate at a portion other than the grooves. This structure enables to improve the reliability of a soldered portion even for small electronic components with about 10 &mgr;m thick electrodes such as chip resistors, chip capacitors, and chip inductors.Type: ApplicationFiled: July 27, 2001Publication date: June 20, 2002Inventors: Hiroyuki Yamada, Takeshi Iseki, Yasuharu Kinoshita