Abstract: There is disclosed an ATM communication apparatus including an SAR module for executing the processing of a low level layer in an ATM communication network, and a processing unit for executing the processing of a high level layer in the ATM communication network, for the purpose of realizing the function of converting an ATM cell which is a unit of information transmission in the ATM communication network, into an IP packet adapted to a communication protocol of a computer network, and the function of converting the IP packet to ATM cells. Segmentation and reassembly of the IP packet is executed in the SAR module. Thus, congestion of data between the SAR module and the processing unit can be reduced, so that the throughput from the input of the ATM cells to the output of the IP packet and from the input of the IP packet to the output of the ATM cells can be elevated.

Abstract: In an ATM communication control device, a cell transmission timing via a virtual channel is determined based on peak rate instructed in a received predetermined ATM cell, such as a received RM cell. Upon determining the transmission timing, a next transmission time for a virtual channel is stored in a CAM, and when a counter value agrees with the stored transmission time, the virtual channel corresponding to an address storing the agreed transmission time is determined as a virtual channel for transmission. The CAM may be replaced by a combination of comparators and a normal storage device.

Abstract: An I/O port enable to intercept the SCSI communications between a SCSI control circuit and host system regardless at the data transmission mode or at data reception mode. When the SCSI communications are intercepted, a system controller transfers data from a main memory to a buffer memory through the SCSI control circuit at the data transmission mode of the SCSI control circuit and performs the self-diagnosis of the SCSI control circuit by comparing data transmitted to the buffer memory with the test data stored in the main memory. At the data reception mode of the SCSI control circuit, the system controller stores data read from the main memory to the buffer memory through the buffer memory control circuit and performs the self-diagnosis of the SCSI control circuit by comparing data read from the I/O port with data stored in the main memory.

Abstract: A disk controller for a disk having spirally formed tracks comprises a buffer memory for temporarily storing write data to be recorded on said disk and read data derived from said disk. A first register temporarily stores current sector information representative of a sector currently accessible, the current sector information being changed in accordance with rotation of said disk. A second register temporarily stores target sector information representative of a sector from which a data read/write operation starts. A comparator compares the current sector information with said target sector information to produce a comparison output signal taking an active level when the current sector information coincides with the target sector information. A memory control unit produces a ready signal taking an active level when the write data is stored in the buffer memory or when the buffer memory has a vacancy for accepting the read data.

Abstract: An error correction circuit comprises a plurality of Galois body operation units coupled in cascade through a bus but operated in parallel. Each of the units includes a Galois body multiplication circuit, a Galois body addition circuit and a plurality of registers, thereby generating and decoding a BCH code.

Abstract: A digital signal processing apparatus with a rate-conversion function has at least two digital filters and a memory. A digital signal stored in the memory is selectively transferred to the at least two digital filters. These digital filters perform a filtering operation in parallel, and the results from each of the digital filters are alternately derived by a multiplexer. Thus, high-speed filtering can be executed. The memory temporarily stores a time-division-multiplexed signal which is sequentially read out of the memory and selectively transferred to the digital filters. Thus, a plurality of digital signals can be filtered by the same digital filters without an increase in hardware elements. Therefore, the digital filter section can be integrated in a single semiconductor chip. A shift register may be used as the memory, whereby a circuit arrangement of the digital filter section can be extremely simplified.

Abstract: A digitalized detection circuit as an envelope detector of an analog input signal is disclosed. This circuit includes an analog-to-digital converter converting the analog input signal into first digital data, storing means for storing second digital data to be outputted, and a comparator comparing the first and second digital data. When the first digital data is equal to or larger (smaller) than the second data, the first digital data is supplied to the storing means, and when the former is smaller (larger) than the latter, the storing means receives cyclically third data that is the second data minus (plus) a predetermined value. A digitalized peak or bottom envelope detector is thereby obtained.

Abstract: In an address indication circuit for use in indicating memory addresses of a random access memory to provide delays necessary for successive channels, channel addresses are determined relative to the memory addresses by assigning a reference number to a leading one of the channels and by successively accumulating the reference number and numbers determined for the delays to decide results of accumulation as the remaining channel addresses. The respective channel addresses are stored in a read-only memory (80) and added by an adder (83) to a base address variable at every time interval to provide memory addresses. When the memory addresses are equal in number to a preselected number, the base address may be produced by a counter (81) carrying out operation between zero and the preselected number less one. The adder adds the reference number to the base address modulo the preselected number.

Abstract: In a decoder responsive to a sequence of interleaved codes and comprising a syndrome generator (20) and a calculating circuit (10) cooperating with the syndrome generator, the interleaved code sequence is reproduced into first and second reproduced sequence which are subjected to first and second error corrections by the use of the syndrome generator and the calculating circuit with reference to check codes included in each reproduced sequence. When the syndrome generator is put into operation for one of the first and the second error corrections, the calculating circuit is operated for the other. Thus, the first and the second error corrections are alternatingly carried out in each of the syndrome generator and the calculating circuit. Preferably, each of the first and the second reproduced sequence is of Reed-Solomon codes.