Abstract: A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit.