Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

Abstract: This invention is to provide a nanodevice, which is combined with an electronic device such as a diode, tunnel device and MOS transistor, integrated circuit and manufacturing method of the nanodevice. A nanodevice includes: a first insulating layer 2; one electrode 5A and the other electrode 5B provided to have a nanogap on the first insulating layer 2; a metal nanoparticle or a functional molecule provided between the one electrode 5A and the other electrode 5B; a second insulating layer 8 provided on the first insulating layer 2, and on the one electrode 5A and the other electrode 5B to embed the metal nanoparticle or the functional molecule. The second insulating layer works as a passivating layer.

Abstract: This invention is to provide a nanodevice, which is combined with an electronic device such as a diode, tunnel device and MOS transistor, integrated circuit and manufacturing method of the nanodevice. A nanodevice includes: a first insulating layer 2; one electrode 5A and the other electrode 5B provided to have a nanogap on the first insulating layer 2; a metal nanoparticle or a functional molecule provided between the one electrode 5A and the other electrode 5B; a second insulating layer 8 provided on the first insulating layer 2, and on the one electrode 5A and the other electrode 5B to embed the metal nanoparticle or the functional molecule. The second insulating layer works as a passivating layer.

Abstract: To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles. An oxide film reducing treatment with hydrogen radicals is carried out for surfaces of lead-out electrodes (5) and bump electrodes (6) on the lead-out electrodes (5) of a semiconductor chip (2) and surfaces of lead-out electrodes (8) of an intermediate substrate (3), and, after that, the bump electrodes (6) of the semiconductor chip (2) and the lead-out electrodes (8) of the intermediate substrate (3) are aligned with each other. After that, a pressure is applied to bond the bump electrodes (6) and the lead-out electrodes (8).

Abstract: A method for controlling a structure of a nano-scale substance may include irradiating a mixture of low-dimensional quantum structures having a nano-scale with an electromagnetic wave in an oxygen atmosphere, to thereby selectively oxidize a low-dimensional quantum structure having a density of states resonating with the electromagnetic wave used for the irradiation. The method allows a low-dimensional quantum structure having a specific structure to be selectively removed from the mixture of low-dimensional quantum structures having a nano-scale.

Abstract: A method for controlling a structure of a nano-scale substance may include irradiating a mixture of low-dimensional quantum structures having a nano-scale with an electromagnetic wave in an oxygen atmosphere, to thereby selectively oxidize a low-dimensional quantum structure having a density of states resonating with the electromagnetic wave used for the irradiation. The method allows a low-dimensional quantum structure having a specific structure to be selectively removed from the mixture of low-dimensional quantum structures having a nano-scale.

Abstract: A method for controlling a structure of a nano-scale substance, which comprises irradiating a mixture of low-dimensional quantum structures having a nano-scale with an electromagnetic wave in an oxygen atmosphere, to thereby selectively oxidize a low-dimensional quantum structure having a density of states resonating with the electromagnetic wave used for the irradiation. The method allows a low-dimensional quantum structure having a specific structure to be selectively disappeared from the mixture of low-dimensional quantum structures having a nano-scale.

Abstract: [Object] To facilitate bonding of articles at a low temperature without degrading electrical contact between the articles. [Means to Realize Object] An oxide film reducing treatment with hydrogen radicals is carried out for surfaces of lead-out electrodes (5) and bump electrodes (6) on the lead-out electrodes (5) of a semiconductor chip (2) and surfaces of lead-out electrodes (8) of an intermediate substrate (3), and, after that, the bump electrodes (6) of the semiconductor chip (2) and the lead-out electrodes (8) of the intermediate substrate (3) are aligned with each other. After that, a pressure is applied to bond the bump electrodes (6) and the lead-out electrodes (8).

Abstract: A semiconductor chip (20) including a protruding electrode (bump) (23) in an external extraction electrode is mounted on a wiring board (10), and a semiconductor chip (30) is mounted on the semiconductor chip (20). Electrical connections between a wiring layer (12) of the wiring board (10) and the protruding electrode (23) of the semiconductor chip (20) and between the protruding electrodes of the semiconductor chips (20) and (30) are established by electrolytic plating. Stable connections between the wiring layer (12) and the protruding electrode (23) and between the protruding electrodes of the semiconductor chips (20) and (30) are established by plating films (24) and (33).

Abstract: A method of an embodiment of the present of the present application is for producing a nano-scale low dimensional quantum structure. The method includes: bringing a catalyst on a substrate into contact with vaporized carbon source, and emitting an electromagnetic wave to the catalyst so as to form single-walled carbon nano-tubes on the catalyst. As a result, it is possible to form the nano-scale low-dimensional quantum structure on a target area.

Abstract: An object of the invention is to provide a high-quality soldering method, by reducing, to a vacuum, the pressure in a vacuum room (2) in which a workpiece (10) having solid solder placed thereon consisting solely of tin or including tin and one or more components selected from silver, lead, copper, bismuth, indium and zinc is disposed. A free-radical gas is generated to remove an oxide film on the solder, and, after that, the generation of the free-radical gas is stopped, and the temperature of the solder is raised to a temperature above the melting point of the solder to melt the solder in the non-oxidizing atmosphere.

Abstract: A method for controlling a structure of a nano-scale substance, which comprises irradiating a mixture of low-dimensional quantum structures having a nano-scale with an electromagnetic wave in an oxygen atmosphere, to thereby selectively oxidize a low-dimensional quantum structure having a density of states resonating with the electromagnetic wave used for the irradiation. The method allows a low-dimensional quantum structure having a specific structure to be selectively disappeared from the mixture of low-dimensional quantum structures having a nano-scale.

Abstract: A semiconductor chip (20) including a protruding electrode (bump) (23) in an external extraction electrode is mounted on a wiring board (10), and a semiconductor chip (30) is mounted on the semiconductor chip (20). Electrical connections between a wiring layer (12) of the wiring board (10) and the protruding electrode (23) of the semiconductor chip (20) and between the protruding electrodes of the semiconductor chips (20) and (30) are established by electrolytic plating. Stable connections between the wiring layer (12) and the protruding electrode (23) and between the protruding electrodes of the semiconductor chips (20) and (30) are established by plating films (24) and (33).

Abstract: A method of producing soft fine metal spheres for semiconductor packaging from a material selected from soft metals and soft alloys. A plurality of fine wires made of the material are arranged in parallel on a flat base plate. Each of the wires has a diameter of not more than 100 .mu.m. The fine wires are cut into wire chips having an equal mass relative to each other and a chip length/chip diameter ratio between 5 and 100 by utilizing a cutting jig having cutting edges which are arranged at a constant pitch. The resulting wire chips are arranged so that the chips are spaced apart a minimum distance sufficient to prevent the chips from merging when melted. The resulting spaced-apart wire chips are heated to a temperature up to but not exceeding 100.degree. C. above the melting point thereof, thereby forming the chips into molten spheres. The resulting molten spheres are cooled, thereby forming solid spheres having a diameter within about 5% of a desired diameter.

Abstract: This invention provides a thin gold-alloy wire for a semiconductor device capable of improving long term reliability of bonding with an electrode and capable of simultaneously accomplishing reduction of a wire bend and wire flow at the time of resin molding and high looping.The thin gold-alloy wire contains 50 to 3000 ppm by weight of Mn and the balance comprising gold and unavoidable impurities. Further, the thin gold-alloy wire comprises any of the following combinations 1, 2, 1+2, 2+3 and 1+2+3 when element groups to be added are classified into the following groups 1 to 3:1 1 to 20 ppm by weight in total of at least one of Be and B;2 1 to 30 ppm by weight in total of at least one of Ca, Sr and rare earth elements; and3 1 to 50 ppm by weight in total of at least oneof In and Tl.The thin gold-alloy wire according to the present invention has high bonding reliability at the bond portion with the electrode on a semiconductor device and can be packaged with high density semiconductor devices.

Abstract: This invention relates to a bonding wire (3) for connecting electrodes of a semiconductor element to outer leads (2). The bonding wire (3) consists of Cu of not less than 1 wt % but less than 5 wt %, and the balance Au and incidental impurities. The bonding wire is superior in rupture strength and bonding strength. Even if the diameter is thinned to about 10 .mu.m, high reliability may be insured for connection.

Abstract: A composite lead frame comprising a lead frame (10), leads (28) supported on a plastic film (22 ') having a device hole (24), and a metal (14, 32) for mounting a semiconductor chip (34) is disclosed. The lead frame (10) has a plurality of inner lead portions (12) each of which is bonded to each of the leads (28), respectively. The metal (14, 32) also supports the leads (28) through the plastic film (22'). The metal (14, 32) may be bonded to the lead frame (10) through an adhesive tape (16), or may be integrated with the lead frame (10). Bonding wires (36) to connect the leads (28) and the semiconductor chip (34) can be easily and securely bonded to the leads (28) in virtue of the metal (14, 32) supporting the leads (28). Additionally, a semiconductor device incorporating the composite lead frame has efficient heat dissipation and reliability by virtue of the metal pad.

Abstract: A method of connecting a TAB tape to a semiconductor chip is disclosed which comprises the steps of preliminarily locating and fixing bumps at positions corresponding to a pattern of electrodes of the semiconductor chip to be connected; and bonding the bumps by thermocompression to the electrodes of the semiconductor chip and the leads of the TAB tape, respectively, so that each electrode of the semiconductor chip is electrically connected to the corresponding lead of the TAB tape through a corresponding one of the bumps. Also disclosed are a bump sheet and a bumped tape to be used in a method of connecting a TAB tape to a semiconductor chip.

Abstract: A method of bonding bumps to leads of a TAB tape comprises the steps of preparing a substrate which is provided with through-holes, each having a size which will not allow the bumps to pass therethrough, at positions corresponding to bonding positions of the leads of the TAB tape where the bumps are to be bonded; provisionally arranging the bumps at positions of the through-holes at one side of the substrate by reducing a pressure in another side of the substrate opposite to said one side thereof to such the bumps in said through-holes; disposing the substrate on which the bumps are provisionally arranged and said TAB tape in such a positional relationship that said bumps face to the bonding positions of the leads of said TAB tape; and bonding the provisionally arranged bumps to the leads at the bonding positions and an apparatus for arranging bumps in a positional relationship corresponding to bonding positions of leads of a TAB tape.