Abstract: A method of making a semiconductor integrated circuit includes forming switches configured to suspend, on a way-specific basis, power supply to ways allocated to one or more RAM macros.

Abstract: A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

Abstract: A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of a row address in a previous cycle and a row address in a current cycle, and a row address decoder that decodes the row address, and outputs a word line select signal to select one of word lines connected to a part of the plurality of memory cells based on the decoded row address, and prevents the output of the word line select signal when the control signal outputted from the comparator is inputted to the row address decoder.

Abstract: A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

Abstract: A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal.