Abstract: A sensor device includes a bridge circuit, a bias circuit, and a detection signal receiving circuit. The bridge circuit includes four sensor elements connected in a bridge. The bias circuit includes an oscillation circuit and an averaging circuit. The oscillation circuit outputs an oscillation signal, in which an output voltage in a first output state and an output voltage in a second output state with temperature dependency repeat alternately at a predetermined ratio. The averaging circuit averages the output voltage of the oscillation circuit and applies the averaged output voltage as a bias voltage to a bias end of the bridge circuit. By applying this voltage, the bias circuit excites the bridge circuit and compensates for a temperature characteristic of the sensitivity by offsetting a temperature fluctuation due to a temperature change in its sensitivity.

Abstract: In a sensor device, a bias circuit includes a bias voltage generation circuit, a regulator circuit, an impedance calculation circuit, and a bias voltage correction circuit. The bias voltage generation circuit generates a bias voltage required to operate the bridge circuit. The regulator circuit applies the bias voltage to the bridge circuit and monitors a bias current supplied to the bridge circuit. The impedance calculation circuit receives a value of the bias voltage and a value of the bias current and calculates an impedance of the bridge circuit. Based on the impedance, the bias voltage correction circuit causes the bias voltage to be corrected to a voltage that compensates for a change in characteristics of the bridge circuit.

Abstract: A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a ? modulation on the analog input signal which is converted into a digital signal.

Abstract: An ultrasonic sensor is provided in which, after output of an excitation signal from a transmission circuit to a drive electrode is stopped, when a suppression control signal subjected to signal amplification by a band variable calculation amplifier is supplied from a reverberant vibration suppression circuit to the drive electrode, reverberant vibration of a piezoelectric body is reduced or prevented in a reverberation suppression time period. In a reception time period after output of the suppression control signal to the drive electrode is stopped, a signal amplification frequency band of the band variable calculation amplifier is varied by a control circuit, and a signal amplification factor of the band variable calculation amplifier in a frequency band of high-frequency noise that occurs within the band variable calculation amplifier is reduced.

Abstract: A comparison circuit includes a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result. The preliminary amplification circuit converts the first input voltage and the second input voltage input with the falling edge timing of a clock signal into a first control signal and a second control signal, respectively that return from the reversal state at respective speeds corresponding to the first input voltage and the second input voltage. The latch circuit compares the first input voltage and the second input voltage according to the first control signal and the second control signal.

Abstract: A comparison circuit includes a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result. The preliminary amplification circuit converts the first input voltage and the second input voltage input with the falling edge timing of a clock signal into a first control signal and a second control signal, respectively that return from the reversal state at respective speeds corresponding to the first input voltage and the second input voltage. The latch circuit compares the first input voltage and the second input voltage according to the first control signal and the second control signal.

Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

Abstract: A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a ? modulation on the analog input signal which is converted into a digital signal.

Abstract: A pseudo resistance circuit includes a first gate voltage adjustment circuit that adjusts respective currents of first and second current sources and also adjusts a gate voltage of a second field effect transistor to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of a first end portion of a reference resistance element and controls a drain voltage of a first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the second field effect transistor and the gate voltage of the first field effect transistor to maintain a constant or substantially constant relationship with each other.

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

Abstract: A pseudo resistance circuit includes a first gate voltage adjustment circuit that adjusts respective currents of first and second current sources and also adjusts a gate voltage of a second field effect transistor to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of a first end portion of a reference resistance element and controls a drain voltage of a first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the second field effect transistor and the gate voltage of the first field effect transistor to maintain a constant or substantially constant relationship with each other.

Abstract: An object of the invention is to provide a physical quantity sensor capable of producing a highly accurate physical quantity detection signal.

Abstract: A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.

Abstract: This invention relates to a leveling device in which a shaft (7) of a card cylinder (6) is supported by a bearing of a card cylinder bracket, base portion of the card cylinder bracket is pivotally attached to a machine frame, and the card cylinder bracket can be rocked between working attitude and leveling attitude. The card cylinder bracket is urged into the leveling attitude by a spring or the like, and it is held in the working attitude and the leveling attitude by a cam or a crank arm which is disposed near the card cylinder (6) and installed to a parallel shaft being in parallel to the cylinder.