Patents by Inventor Yasuhiko Akaike
Yasuhiko Akaike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705344Abstract: A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.Type: GrantFiled: August 18, 2021Date of Patent: July 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masakatsu Suzuki, Haruhiko Harada, Yasuhiko Akaike
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Publication number: 20220068668Abstract: A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.Type: ApplicationFiled: August 18, 2021Publication date: March 3, 2022Inventors: Masakatsu SUZUKI, Haruhiko HARADA, Yasuhiko AKAIKE
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Patent number: 11031254Abstract: After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.Type: GrantFiled: September 27, 2019Date of Patent: June 8, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiko Akaike
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Patent number: 11024599Abstract: The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm.Type: GrantFiled: October 16, 2019Date of Patent: June 1, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Hayashi, Yasuhiko Akaike
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Publication number: 20200185353Abstract: The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm.Type: ApplicationFiled: October 16, 2019Publication date: June 11, 2020Inventors: Ryo Hayashi, Yasuhiko Akaike
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Publication number: 20200144075Abstract: After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.Type: ApplicationFiled: September 27, 2019Publication date: May 7, 2020Inventor: Yasuhiko AKAIKE
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Patent number: 9853023Abstract: A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.Type: GrantFiled: January 3, 2017Date of Patent: December 26, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Akaike, Kenya Kobayashi, Yukie Nishikawa
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Publication number: 20170117269Abstract: A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.Type: ApplicationFiled: January 3, 2017Publication date: April 27, 2017Inventors: Yasuhiko AKAIKE, Kenya KOBAYASHI, Yukie NISHIKAWA
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Publication number: 20170077218Abstract: Provided is a semiconductor device including a first electrode, a second electrode, a semiconductor substrate having a first plane, a second plane, a first conductivity-type first region, and a plurality of second conductivity-type second regions provided around the first electrode, the second regions being in contact with the first plane, at least a portion of the semiconductor substrate being provided between the first electrode and the second electrode, a first insulating film provided on or above the second regions, the first insulating film including positive charges, and a second insulating film provided on or above the second regions, second insulating film including negative charges.Type: ApplicationFiled: February 12, 2016Publication date: March 16, 2017Inventors: Yukie Nishikawa, Yasuhiko Akaike, Masaki Okazaki
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Patent number: 9570439Abstract: A semiconductor device includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a first electrode, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The first electrode is provided on the second semiconductor region. The third semiconductor region is provided on the first electrode. The fourth semiconductor region is provided on the third semiconductor region. The conductive portion is surrounded by the third semiconductor region and an intervening insulation portion and is electrically connected to the first electrode.Type: GrantFiled: August 31, 2015Date of Patent: February 14, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Akaike, Kenya Kobayashi, Yukie Nishikawa
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Publication number: 20160268254Abstract: A semiconductor device includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a first electrode, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The first electrode is provided on the second semiconductor region. The third semiconductor region is provided on the first electrode. The fourth semiconductor region is provided on the third semiconductor region. The conductive portion is surrounded by the third semiconductor region and an intervening insulation portion and is electrically connected to the first electrode.Type: ApplicationFiled: August 31, 2015Publication date: September 15, 2016Inventors: Yasuhiko AKAIKE, Kenya KOBAYASHI, Yukie Nishikawa
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Patent number: 9318664Abstract: According to one embodiment, a semiconductor light emitting element includes: a support substrate; a bonding layer provided on the support substrate; an LED layer provided on the bonding layer; and a buffer layer softer than the bonding layer. The buffer layer is placed in one of between the support substrate and the bonding layer and between the bonding layer and the LED layer.Type: GrantFiled: September 14, 2012Date of Patent: April 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Nunotani, Yasuhiko Akaike, Yoshinori Natsume, Kazuyoshi Furukawa
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Publication number: 20160049484Abstract: A semiconductor device includes a second conductivity-type second semiconductor layer selectively provided on a first conductivity-type first semiconductor layer, a first conductivity-type third semiconductor layer provided on the second semiconductor layer, and at least one control electrode that is spaced from the second semiconductor layer and the third semiconductor layer by an insulating film. In addition, the semiconductor device further includes a second conductivity-type fourth semiconductor layer provided on a side of the control electrode opposite to a side thereof where the second semiconductor layer is located, and a semiconductor region that is provided between the first semiconductor layer and the fourth semiconductor layer, the first semiconductor layer making contact in the insulating film at the bottom of the control electrode, and containing at least one type of electrically inactive element in at least any one of the first semiconductor layer and the fourth semiconductor layer.Type: ApplicationFiled: March 1, 2015Publication date: February 18, 2016Inventors: Yukie NISHIKAWA, Yasuhiko AKAIKE
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Patent number: 9147798Abstract: According to one embodiment, a semiconductor light emitting element includes a light emitting element includes a semiconductor stacked body including a light emitting layer, a reflection layer, a support substrate, a first bonding electrode and a second bonding electrode. The reflection layer is made of a metal and has a first surface and a second surface opposite to the first surface. The semiconductor stacked body is provided on a side of the first surface of the reflection layer. The first bonding electrode is provided between the second surface and the support substrate and includes a convex portion projected toward the support substrate and a bottom portion provided around the convex portion in plan view. The second bonding electrode includes a concave portion fitted in the convex portion of the first bonding electrode and is capable of bonding the support substrate and the first bonding electrode.Type: GrantFiled: March 15, 2012Date of Patent: September 29, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Akaike, Yoshinori Natsume, Shinji Nunotani, Kazuyoshi Furukawa
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Publication number: 20150262813Abstract: According to one embodiment, a semiconductor device includes a first electrode on a surface of a semiconductor layer and a plurality of second electrodes on the first electrode. Each second electrode has a shape in a plane that is parallel to the surface of the semiconductor layer having dimensions of 50 micrometers or less. A resin layer is between the plurality of second electrodes, and has a modulus that is lower than a modulus of the second electrodes.Type: ApplicationFiled: August 29, 2014Publication date: September 17, 2015Inventors: Motoya KISHIDA, Yukie NISHIKAWA, Nobuhiro TAKAHASHI, Yasuhiko AKAIKE
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Publication number: 20150249180Abstract: According to one embodiment, a semiconductor light emitting element includes a light emitting element includes a semiconductor stacked body including a light emitting layer, a reflection layer, a support substrate, a first bonding electrode and a second bonding electrode. The reflection layer is made of a metal and has a first surface and a second surface opposite to the first surface. The semiconductor stacked body is provided on a side of the first surface of the reflection layer. The first bonding electrode is provided between the second surface and the support substrate and includes a convex portion projected toward the support substrate and a bottom portion provided around the convex portion in plan view. The second bonding electrode includes a concave portion fitted in the convex portion of the first bonding electrode and is capable of bonding the support substrate and the first bonding electrode.Type: ApplicationFiled: April 29, 2015Publication date: September 3, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiko AKAIKE, Yoshinori Natsume, Shinji Nunotani, Kazuyoshi Furukawa
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Patent number: 8969157Abstract: According to one embodiment, in a method of a semiconductor device, a trench is formed in the direction of a lower surface from an upper surface of a semiconductor layer. A first insulating film is formed to cover an inner surface of the trench. An electrode material is formed to fill the trench and cover the upper surface of the semiconductor layer. The electrode material is selectively removed except a portion of the electrode material to fill the trench and a portion of the electrode material to cover an opening of the trench. The first insulating film to cover an upper portion of the trench is removed. The portions of the electrode material to fill the trench and cover the opening of the trench are etched back to form a first electrode at a lower portion of the trench.Type: GrantFiled: September 10, 2013Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhiro Takahashi, Yukie Nishikawa, Yasuhiko Akaike
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Publication number: 20140287574Abstract: According to one embodiment, in a method of a semiconductor device, a trench is formed in the direction of a lower surface from an upper surface of a semiconductor layer. A first insulating film is formed to cover an inner surface of the trench. An electrode material is formed to fill the trench and cover the upper surface of the semiconductor layer. The electrode material is selectively removed except a portion of the electrode material to fill the trench and a portion of the electrode material to cover an opening of the trench. The first insulating film to cover an upper portion of the trench is removed. The portions of the electrode material to fill the trench and cover the opening of the trench are etched back to form a first electrode at a lower portion of the trench.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nobuhiro Takahashi, Yukie Nishikawa, Yasuhiko Akaike
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Patent number: 8829488Abstract: Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.Type: GrantFiled: August 27, 2012Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
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Patent number: 8816378Abstract: According to one embodiment, a light emitting element, includes: a semiconductor stacked body including a light emitting layer; a first upper electrode being connected directly to the semiconductor stacked body; at least one second upper electrode extending from the first upper electrode, the at least one second upper electrode being connected to the semiconductor stacked body via a first contact layer; a lower electrode; a transparent conductive layer; an intermediate film containing oxygen provided between the semiconductor stacked body and the transparent conductive layer; a light reflecting layer; and a current-blocking layer, at least one slit being provided selectively in the current-blocking layer as viewed from a direction perpendicular to a major surface of the light emitting layer.Type: GrantFiled: June 27, 2013Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Nunotani, Yasuhiko Akaike, Kayo Inoue, Katsufumi Kondo, Tokuhiko Matsunaga