Patents by Inventor Yasuhiko Akamatsu

Yasuhiko Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935936
    Abstract: [Object] It is an object of the present invention to provide an aluminum alloy film having excellent bending resistance and heat resistance, and a thin film transistor including the aluminum alloy film. [Solving Means] In order to achieve the above-mentioned object, an aluminum alloy film according to an embodiment of the present invention includes: an Al pure metal that includes at least one type of a first additive element selected from the group consisting of Zr, Sc, Mo, Y, Nb, and Ti. A content of the first additive element is 0.01 atomic % or more and 1.0 atomic % or less. Such an aluminum alloy film has excellent bending resistance and excellent heat resistance. Further, also etching can be performed on the aluminum alloy film.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 19, 2024
    Assignee: ULVAC, INC.
    Inventors: Yuusuke Ujihara, Motoshi Kobayashi, Yasuhiko Akamatsu, Tomohiro Nagata, Ryouta Nakamura, Junichi Nitta, Yasuo Nakadai
  • Publication number: 20210226028
    Abstract: [Object] It is an object of the present invention to provide an aluminum alloy film having excellent bending resistance and heat resistance, and a thin film transistor including the aluminum alloy film. [Solving Means] In order to achieve the above-mentioned object, an aluminum alloy film according to an embodiment of the present invention includes: an Al pure metal that includes at least one type of a first additive element selected from the group consisting of Zr, Sc, Mo, Y, Nb, and Ti. A content of the first additive element is 0.01 atomic % or more and 1.0 atomic % or less. Such an aluminum alloy film has excellent bending resistance and excellent heat resistance. Further, also etching can be performed on the aluminum alloy film.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 22, 2021
    Inventors: Yuusuke UJIHARA, Motoshi KOBAYASHI, Yasuhiko AKAMATSU, Tomohiro NAGATA, Ryouta NAKAMURA, Junichi NITTA, Yasuo NAKADAI
  • Publication number: 20210140032
    Abstract: [Object] It is an object of the present invention to provide an aluminum alloy target capable of forming an aluminum alloy film having excellent bending resistance and heat resistance, and a method of producing the aluminum alloy target. [Solving Means] In order to achieve the above-mentioned object, an aluminum alloy target according to an embodiment of the present invention includes: an Al pure metal that includes at least one type of a first additive element selected from the group consisting of Zr, Sc, Mo, Y, Nb, and Ti. A content of the first additive element is 0.01 atomic % or more and 1.0 atomic % or less. The aluminum alloy film formed using such an aluminum alloy target has excellent bending resistance and excellent heat resistance. Further, also etching can be performed on the aluminum alloy film.
    Type: Application
    Filed: March 28, 2019
    Publication date: May 13, 2021
    Inventors: Ryouta NAKAMURA, Tomohiro NAGATA, Yasuhiko AKAMATSU, Motoshi KOBAYASHI, Yuusuke UJIHARA, Yasuo NAKADAI, Junichi NITTA
  • Patent number: 8221594
    Abstract: The present invention is to provide a magnetron sputtering technique for forming a film having an even film thickness distribution for a long period of time. A magnetron sputtering apparatus of the present invention includes a vacuum chamber, a cathode part provided in the vacuum chamber, the cathode part holding a target on the front side thereof and having a backing plate to hold a plurality of magnets on the backside thereof, and a direct-current power source that supplies direct-current power to the cathode part. A plurality of control electrodes, which independently controls potentials, is provided in a discharge space on the side of the target with respect to the backing plate.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 17, 2012
    Assignee: Ulvac, Inc.
    Inventors: Yasuhiko Akamatsu, Kyuzo Nakamura, Motoshi Kobayashi, Junya Kiyota, Tomiyuki Yukawa, Masaki Takei, Yuuichi Oishi, Makoto Arai, Satoru Ishibashi
  • Patent number: 8172993
    Abstract: In a magnetron sputtering apparatus an arrangement is made such that the peripheral portion of a target is uniformly eroded to attain a high efficiency in target utilization and, in addition, that an abnormal discharging hardly occurs to thereby enable satisfactory thin film forming. A magnet assembly is provided behind a target that is disposed opposite to the process substrate. This magnet assembly has a central magnet that is disposed linearly along the longitudinal direction, and a peripheral magnet that is disposed so as to enclose the periphery of the central magnet, while changing the polarity on the side of the target. At this time, among the respective magnetic fluxes generated between the central magnet and the peripheral magnet at the longitudinally end portions of the magnet assembly, the position at which the vertical component of the magnetic field becomes zero is locally shifted to the central magnet within a certain range.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: May 8, 2012
    Assignee: Ulvac, Inc.
    Inventors: Yasuhiko Akamatsu, Tatsunori Isobe, Makoto Arai, Junya Kiyota, Takashi Komatsu
  • Publication number: 20110198213
    Abstract: [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. [Solving Means] The sputtering apparatus according to the present invention sputters target portions Tc1 to Tc5, which are arranged in an inside of a vacuum chamber, along the arrangement direction thereof in sequence, to thereby form a thin-film on a surface of a substrate 10. With this, rate at which sputtered particles enter the surface of the substrate in a direction oblique to the surface of the substrate is increased, and hence it is possible to achieve a reduction of the damage of the base layer.
    Type: Application
    Filed: October 9, 2009
    Publication date: August 18, 2011
    Applicant: ULVAC, INC.
    Inventors: Takaomi Kurata, Junya Kiyota, Makoto Arai, Yasuhiko Akamatsu, Satoru Ishibashi, Kazuya Saito
  • Publication number: 20110201150
    Abstract: [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. [Solving Means] The sputtering apparatus 100 includes a conveying mechanism, a first target Tc1, a second target (Tc2 to Tc5), and a sputtering means. The conveying mechanism conveys a supporting portion, which is arranged in an inside of a vacuum chamber and supports a substrate, linearly along a conveying surface parallel to the surface to be processed of the substrate. The first target Tc1 is opposed to the conveying surface with a first space therebetween. The second target (Tc2 to Tc5) is arranged on a downstream side in a conveying direction of the substrate with respect to the first target Tc1, and is opposed to the conveying surface with a second space smaller than the first space therebetween. The sputtering means sputters each target.
    Type: Application
    Filed: October 9, 2009
    Publication date: August 18, 2011
    Applicant: ULVAC, INC.
    Inventors: Takaomi Kurata, Junya Kiyota, Makoto Arai, Yasuhiko Akamatsu, Satoru Ishibashi, Kazuya Saito
  • Publication number: 20110195562
    Abstract: [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. [Solving Means] A sputtering apparatus according to an embodiment of the present invention is a sputtering apparatus for forming a thin-film on a surface to be processed of a substrate 10, and includes a vacuum chamber 61, a supporting portion 93, a target 80, and a magnet 83. The magnet 83 generates plasma forming a region to be sputtered 80a, and moves the region to be sputtered 80abetween a first position in which the region to be sputtered 80a is not opposed to the surface to be processed and a second position in which the region to be sputtered is opposed to the surface to be processed. With this, it is possible to weaken incident energy of sputtered particles incident on the surface to be processed of the substrate 10 from the region to be sputtered 80a, and to protect the base layer.
    Type: Application
    Filed: October 14, 2009
    Publication date: August 11, 2011
    Applicant: ULVAC, INC.
    Inventors: Takaomi Kurata, Junya Kiyota, Makoto Arai, Yasuhiko Akamatsu, Satoru Ishibashi, Kazuya Saito
  • Publication number: 20110180402
    Abstract: To provide a vacuum processing apparatus capable of supporting and conveying a substrate by a method suitable for a processing content in each processing step and capable of suppressing various mechanisms provided within a processing chamber from being adversely affected. More particularly, the CVD chamber of the apparatus is configured to be horizontal, and hence the above-mentioned problem can be solved. Further, by configuring a sputtering apparatus as the vertical type processing apparatus, problems with abnormal electrical discharge can be solved.
    Type: Application
    Filed: October 7, 2009
    Publication date: July 28, 2011
    Applicant: ULVAC, INC.
    Inventors: Takaomi Kurata, Junya Kiyota, Makoto Arai, Yasuhiko Akamatsu, Satoru Ishibashi, Shin Asari, Kazuya Saito, Shigemitsu Sato, Masashi Kikuchi
  • Publication number: 20110048926
    Abstract: The present invention is to provide a magnetron sputtering technique for forming a film having an even film thickness distribution for a long period of time. A magnetron sputtering apparatus of the present invention includes a vacuum chamber, a cathode part provided in the vacuum chamber, the cathode part holding a target on the front side thereof and having a backing plate to hold a plurality of magnets on the backside thereof, and a direct-current power source that supplies direct-current power to the cathode part. A plurality of control electrodes, which independently controls potentials, is provided in a discharge space on the side of the target with respect to the backing plate.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 3, 2011
    Applicant: ULVAC, INC.
    Inventors: Yasuhiko AKAMATSU, Kyuzo NAKAMURA, Motoshi KOBAYASHI, Junya KIYOTA, Tomiyuki YUKAWA, Masaki TAKEI, Yuuichi OISHI, Makoto ARAI, Satoru ISHIBASHI
  • Patent number: 7863125
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Publication number: 20100051454
    Abstract: In a magnetron sputtering apparatus an arrangement is made such that the peripheral portion of a target is uniformly eroded to attain a high efficiency in target utilization and, in addition, that an abnormal discharging hardly occurs to thereby enable satisfactory thin film forming. A magnet assembly is provided behind a target that is disposed opposite to the process substrate. This magnet assembly has a central magnet that is disposed linearly along the longitudinal direction, and a peripheral magnet that is disposed so as to enclose the periphery of the central magnet, while changing the polarity on the side of the target. At this time, among the respective magnetic fluxes generated between the central magnet and the peripheral magnet at the longitudinally end portions of the magnet assembly, the position at which the vertical component of the magnetic field becomes zero is locally shifted to the central magnet within a certain range.
    Type: Application
    Filed: November 13, 2007
    Publication date: March 4, 2010
    Inventors: Yasuhiko Akamatsu, Tatsunori Isobe, Makoto Arai, Junya Kiyota, Takashi Komatsu
  • Publication number: 20090263945
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Application
    Filed: June 26, 2009
    Publication date: October 22, 2009
    Applicant: Renesas Technology Corp.,
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Patent number: 7569890
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Publication number: 20070210352
    Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same, and is intended to keep the electrical resistance of source/drain regions at a low level while preventing diffusion of impurities from a semiconductor film and a sidewall. In order to achieve these objects, the semiconductor device of the present invention is configured as follows. That is, the semiconductor device includes a semiconductor substrate, a gate structure, source/drain regions, a first diffusion preventive film and a sidewall. An insulation film, a second diffusion preventive film and a semiconductor film are stacked from to top in this order to form the gate structure. The semiconductor film contains impurities. The first diffusion preventive film covers a side surface of the gate structure, and also covers the semiconductor substrate while exposing at least a part of the source/drain regions. The sidewall is in contact with the source/drain regions while covering the first diffusion preventive film.
    Type: Application
    Filed: April 6, 2005
    Publication date: September 13, 2007
    Inventors: Yasuhiko Akamatsu, Saifon Son, Shinpei Tsujikawa
  • Publication number: 20060273401
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Application
    Filed: April 24, 2006
    Publication date: December 7, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura