Abstract: A semiconductor device includes a logic circuit, a memory circuit having a plurality of first static memory cells formed by a transistor on the semiconductor substrate, a monitor circuit having a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified, and a bus coupled with the logic circuit, the memory circuit and the monitor circuit, wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell.

Abstract: A semiconductor device includes a logic circuit, a memory circuit having a plurality of first static memory cells formed by a transistor on the semiconductor substrate, a monitor circuit having a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified, and a bus coupled with the logic circuit, the memory circuit and the monitor circuit, wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell.

Abstract: A semiconductor device suitable for predicting failures is provided. A semiconductor device including a logic circuit and a static memory having a plurality of first static memory cells formed on a semiconductor substrate, further includes a monitor memory circuit having a second static memory cell formed on the semiconductor substrate, and a monitor circuit MON applying stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified.

Abstract: A semiconductor device suitable for predicting failures is provided. A semiconductor device including a logic circuit and a static memory having a plurality of first static memory cells formed on a semiconductor substrate, further includes a monitor memory circuit having a second static memory cell formed on the semiconductor substrate, and a monitor circuit MON applying stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified.

Abstract: A memory device redundant repair analysis method, recording medium and apparatus allowing a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules. It is possible to provide a memory device redundant repair analysis method, recording medium and apparatus that allow a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules by carrying out processing of finally merging a plurality of repair codes corresponding to respective rules obtained by applying a plurality of redundant repair analysis rules into one code.

Abstract: A semiconductor device trimming method or apparatus is proposed for use with a semiconductor device which includes at least a regular cell array, a spare cell array, a fuse array, and a spare decoder. In the method or apparatus, a trimming table is prepared which lists all address modes of address signals for row or column address lines to be replaced in the regular cell array and the blow mode of the fuse array corresponding to each of the address modes. Then, fuses are selectively blown in the fuse array according to the blow mode corresponding to row or column lines of which the selection has been inhibited in the regular cell array in accordance with the trimming table. The spare decoder inhibits selection of cells in the regular cell array and permit selection of cells on the spare lines in the spare cell array in order to replace the inhibited row or column lines in the regular cell array.

Abstract: Shmoo conditions are set in a Shmoo plot tool and Shmoo plot is started. Initial parameter values are set in tester hardware. A test is performed by using set parameter values. A step in which fail information that is produced as a result of the test is transferred to a relief analysis apparatus. The relief analysis apparatus performs a relief analysis on defective bits. A result of the relief analysis is transferred to the Shmoo plot tool. The Shmoo plot tool outputs a result of the relief analysis as Shmoo data. The step of performing the test and the following steps are repeated while the set parameter values are changed.

Abstract: An apparatus and method for generating a laser trimming program without causing errors due to development by human hands in a time that does not depend on experiences etc. of a person who generates a program, as well as a recording medium on which a program for execution of such a method is recorded and a laser trimming apparatus using such a program. Fuse coordinate calculation programs are stored in advance in a coordinate calculation program database on a memory core basis and a common portion of an LT program is stored in advance in a common program database. At the time of generating an LT program, type information of a memory core incorporated in a target IC chip is input and a corresponding fuse coordinate calculation program is selected from the fuse coordinate calculation programs stored in the coordinate calculation program database and then loaded.

Abstract: A memory device redundant repair analysis method, recording medium and apparatus allowing a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules. It is possible to provide a memory device redundant repair analysis method, recording medium and apparatus that allow a redundant repair analysis method for a memory device with a plurality of redundant repair analysis rules by carrying out processing of finally merging a plurality of repair codes corresponding to respective rules obtained by applying a plurality of redundant repair analysis rules into one code.

Abstract: A semiconductor device trimming method or apparatus is proposed for use with a semiconductor device which includes at least a regular cell array, a spare cell array, a fuse array, and a spare decoder. In the method or apparatus, a trimming table is prepared which lists all address modes of address signals for row or column address lines to be replaced in the regular cell array and the blow mode of the fuse array corresponding to each of the address modes. Then, fuses are selectively blown in the fuse array according to the blow mode corresponding to row or column lines of which the selection has been inhibited in the regular cell array in accordance with the trimming table. The spare decoder inhibits selection of cells in the regular cell array and permit selection of cells on the spare lines in the spare cell array in order to replace the inhibited row or column lines in the regular cell array.

Abstract: An apparatus and method for generating a laser trimming program without causing errors due to development by human hands in a time that does not depend on experiences etc. of a person who generates a program, as well as a recording medium on which a program for execution of such a method is recorded and a laser trimming apparatus using such a program. Fuse coordinate calculation programs are stored in advance in a coordinate calculation program database on a memory core basis and a common portion of an LT program is stored in advance in a common program database. At the time of generating an LT program, type information of a memory core incorporated in a target IC chip is input and a corresponding fuse coordinate calculation program is selected from the fuse coordinate calculation programs stored in the coordinate calculation program database and then loaded.

Abstract: A burn-in apparatus includes burn-in boards for holding semiconductor devices through air suction and for electrically connecting them to external equipment. Since the semiconductor devices are held on the burn-in boards for electrical connection through air suction, sockets are not necessary to hold them on the boards which reduces costs. Further, the leads of semiconductor devices, which have conventionally been susceptible to bending when inserted into or extracted from the sockets, can be protected.