Abstract: The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened.

Abstract: When a CPU is processing a first task by using an accelerator for use in image processing, if a request for allocating the accelerator to a process of a second task is issued, the CPU sets an interruption flag when the process of the second task is prioritized over a process of the first task, and the accelerator is allowed to be used for the process of the second task when a state in which the interruption flag is set is detected at a timing predetermined in accordance with a process stage of the accelerator for the first task. Since the timing of detecting the set interruption flag is determined in accordance with a progress state of the process of the task to be interrupted, task switching can be made at a timing of reducing overhead for save and return for the process of the task to be interrupted.

Abstract: The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened.

Abstract: A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.

Abstract: A wait signal formed by a program wait circuit incorporated in a microprocessor is transmitted to outside circuitry, such as a slave microprocessor or a direct memory access control device. Thereby an outside device assumes the functions of bus master which is incorporated into a wait operation for access to a memory unit. With such a construction, a microcomputer system comprising a plurality of devices to be made into a bus mask can be simplified.