Patents by Inventor Yasuhiko Inada

Yasuhiko Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer and method for manufacturing semiconductor device
    Patent number: 9508559
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
  • SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20140110712
    Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.
    Type: Application
    Filed: September 18, 2013
    Publication date: April 24, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, MITSUFUMI NAOE, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya SASHIDA
  • Semiconductor integrated circuit and designing method for same
    Patent number: 7123084
    Abstract: A power supply cell is arranged in the corner of a rectangular semiconductor chip. A first or second power supply voltage is supplied to a pad of the power supply cell. A first connecting line of the power supply cell connects a first power supply line in an input/output cell area to a first power supply line in a power supply line area. A second connecting line of the power supply cell connects a second power supply line in the input/output cell area to a second power supply line in the power supply line area. A leadout line of the power supply cell connects the first or second connecting line to the pad.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: October 17, 2006
    Assignee: Fujitsu Limited
    Inventors: Nobuaki Tomisato, Yasuhiko Inada
  • Semiconductor integrated circuit and designing method for same
    Publication number: 20050285668
    Abstract: A power supply cell is arranged in the corner of a rectangular semiconductor chip. A first or second power supply voltage is supplied to a pad of the power supply cell. A first connecting line of the power supply cell connects a first power supply line in an input/output cell area to a first power supply line in a power supply line area. A second connecting line of the power supply cell connects a second power supply line in the input/output cell area to a second power supply line in the power supply line area. A readout line of the power supply cell connects the first or second connecting line to the pad.
    Type: Application
    Filed: October 15, 2004
    Publication date: December 29, 2005
    Inventors: Nobuaki Tomisato, Yasuhiko Inada
  • Method of designing semiconductor integrated circuit
    Publication number: 20020047789
    Abstract: A method of designing a semiconductor integrated circuit includes the steps of generating a cell that includes a flip-flop and backup transistors, designing a circuit by use of the cell, and adjusting a timing by connecting the backup transistors to the flip-flop if there is a need to adjust timing of the flip-flop.
    Type: Application
    Filed: February 21, 2001
    Publication date: April 25, 2002
    Inventors: Yasuhiko Inada, Daisuke Miura, Masayuki Okamoto, Mitsuaki Nagasaka, Toshio Arakawa