Abstract: A microprocessor comprises an execution controller for storing a transfer source address and a transfer destination address and for generating a transfer start signal, and a data controller responding to the transfer start signal so as to continuously and repeatedly perform a storing of a transfer data and a transfer of the stored data to a transfer destination, while inhibiting execution of the execution controller during a period of execution of the data transfer. In addition, a counter circuit is provided to count the number of items of data which have been transferred by the data controller. When the data transfer has been completed, the inhibition of the execution of the execution controller is cancelled, and the transfer source address and the transfer destination address in the execution controller is modified in accordance with the number of items of data counted by the counter circuit.

Abstract: A microprogram controller advances the initiation of a string of microinstructions for certain macroinstructions to enhance the overall speed of instruction execution. The microprogram controller includes a memory (50) for storing microinstructions and a generator (30) for generating an initial microinstruction of a certain macroinstruction. A selector (60) selects one of a microinstruction read out of the memory and the initial microinstruction from the generator and latches the selected microinstruction in a microinstruction register (70). The initial microinstruction from the generator is first latched into the register and executed while a succeeding microinstruction is read out of the memory.

Abstract: A plurality of gates are arranged between a coincidence circuit and a group of comparators which compare data outputted by a processor's output buffers, and data inputted to the processor via terminals during a monitor mode. An invalid byte information generator is connected to the gates and applies a signal selected to mask the effects of write instructions being executed on an incomplete word and therefore prevents the generation of an erroneous mismatch signal.

Abstract: A plurality of first selectors are connected to a branch condition taken/non-taken decision circuit, and a second selector is connected to the first selector. Among branch condition taken/non-taken signals, at least one signal is common to the first selectors. Consequently, the step number of microinstruction to realize a macroinstructions is decreased, and the executing time of the macroinstruction is shortened.

Abstract: In a division circuit, a dividend register (7) and a remainder register (14) are connected so that a bit in the MSB of the former is shifted to the LSB of the latter. Higher bits of an N-bit divisor are monitored by a detector (18) and a zero-detect (ZD) signal is generated when they are all "0"s. In the presence of the ZD signal, subtraction is performed by an N/2-bit subtractor (28) between lower-bit data of a divisor and data in the remainder register and, in the absence of the ZD signal, first subtraction is performed between lower-bit data of the divisor and higher-bit data of the dividend register (7) and second subtraction is performed between higher-bit data of the divisor register and data in the remainder register (14). A "1" is written into the LSB of the dividend register (7) either in response to a "1" in the MSB of the remainder register (14) or when no borrow results from subtractions.