Patents by Inventor Yasuhiko Kouno

Yasuhiko Kouno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7051724
    Abstract: An igniter of the present invention has an insulated gate semiconductor device having a collector terminal, an emitter terminal and a gate terminal, a current control circuit which limits current by controlling voltage at the gate terminal when current for flowing through the insulated gate semiconductor device exceeds a fixed value, a voltage monitor circuit for detecting a potential of the collector, and a control current adjusting circuit for controlling current which flows through the gate terminal by receiving output from the voltage monitor circuit.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 30, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junpei Uruno, Yasuhiko Kouno
  • Patent number: 6821867
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can realize fine processing while preventing a warp of a semiconductor wafer. In forming a plurality of semiconductor elements on a semiconductor wafer, grooves for attenuating stress are formed in scribe regions defined between semiconductor element forming regions. Here, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain in the scribe regions. On the alignment pattern forming regions of the scribe regions, an alignment pattern or a TEG pattern which is used in a photolithography step is formed.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyoshi Matsuura, Yasuhiko Kouno, Hideo Miura, Masaharu Kubo
  • Publication number: 20040216724
    Abstract: An igniter of the present invention has an insulated gate semiconductor device having a collector terminal, an emitter terminal and a gate terminal, a current control circuit which limits current by controlling voltage at the gate terminal when current for flowing through the insulated gate semiconductor device exceeds a fixed value, a voltage monitor circuit for detecting a potential of the collector, and a control current adjusting circuit for controlling current which flows through the gate terminal by receiving output from the voltage monitor circuit.
    Type: Application
    Filed: December 22, 2003
    Publication date: November 4, 2004
    Inventors: Junpei Uruno, Yasuhiko Kouno
  • Patent number: 6803294
    Abstract: Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: October 12, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Yasuhiko Kouno, Hideo Miura, Nobuyoshi Matsuura, Masaharu Kubo
  • Publication number: 20030216009
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can realize fine processing while preventing a warp of a semiconductor wafer. In forming a plurality of semiconductor elements on a semiconductor wafer, grooves for attenuating stress are formed in scribe regions defined between semiconductor element forming regions. Here, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain in the scribe regions. On the alignment pattern forming regions of the scribe regions, an alignment pattern or a TEG pattern which is used in a photolithography step is formed.
    Type: Application
    Filed: April 24, 2003
    Publication date: November 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Nobuyoshi Matsuura, Yasuhiko Kouno, Hideo Miura, Masaharu Kubo
  • Publication number: 20030215985
    Abstract: Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.
    Type: Application
    Filed: April 15, 2003
    Publication date: November 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiko Kouno, Hideo Miura, Nobuyoshi Matsuura, Masaharu Kubo