Abstract: A method for accessing a memory of a multi-core system, a related apparatus, a system, and a storage medium involve obtaining data from a system memory according to a prefetch instruction, and sending a message to a core that carries the to-be-accessed data. Each segment of data is stored in an intra-core cache based on the prefetch instruction.

Abstract: A method for accessing a memory of a multi-core system, a related apparatus, a system, and a storage medium involve obtaining data from a system memory according to a prefetch instruction, sending a message to a core that carries the to-be-accessed data. Each segment of data is stored in an intra-core cache based on the prefetch instruction.

Abstract: A data processing device includes a two-dimensional structure including a plurality of stages in a vertical direction, the stages each including basic units in a horizontal direction such that the number of the basic units is equal to the number of ways. The basic units each includes a memory block having a plurality of ports, an address generator for the ports of the memory block, and a calculation unit.

Abstract: A data processing device includes a two-dimensional structure including a plurality of stages in a vertical direction, the stages each including basic units in a horizontal direction such that the number of the basic units is equal to the number of ways. The basic units each includes a memory block having a plurality of ports, an address generator for the ports of the memory block, and a calculation unit.

Abstract: A method and apparatus is provided for significantly speeding-up program execution in a data processing device. The data processing device is provided with a specialized instruction region storage section comprising content addressable memory (CAM) and random access memory (RAM) that operatively functions as an instruction sequence reuse table which is capable of registering/storing sequences of program instructions and corresponding instruction sequence output data as input/output (I/O) groups for potential future use in place of re-executing identical portions of program code.

Abstract: Provided is a data processing device (101) which can execute more number of instructions in parallel. The data processing device (101) includes: a first register file section (110) including plural registers; a second register file section (210) including plural registers associated with the respective registers of the first register file section (110); a first calculation device (120) executing a calculation using data read from the first register file section (110); and a second calculation device (220). The first register file section (110) transfers data held by its registers, to their respective registers in the second register file section (210). The first calculation device (120) transfers its holding calculation result to the second calculation device (220). The second calculation device (220) executes a calculation using at least one of data read from the registers in the second register file section (210) and the calculation result of the first calculation device (120).

Abstract: A dependence relationship storage unit M indicates from which input address and input value each of the output addresses and output values derives. An inter-line AND comparator MR performs AND between each of the line components stored in the dependence relationship storage unit M and sets an I/O group including an output pattern containing at least one output address and output value and an input pattern containing at least one input address and input value. Thus, it is possible to provide a data processing device capable of registering an I/O group appropriate for reuse in instruction section storage means.

Abstract: A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and high in expandability and besides the time required for adjustment of components is reduced significantly to reduce the man-hours for arrangement significantly to reduce the man-hours for development significantly and the same basic parts are used so as to achieve augmentation of the yield and promote reduction of the production cost.

Abstract: A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and high in expandability and besides the time required for adjustment of components is reduced significantly to reduce the man-hours for arrangement significantly to reduce the man-hours for development significantly and the same basic parts are used so as to achieve augmentation of the yield and promote reduction of the production cost.

Abstract: An emulation apparatus and method in which software containing both instructions and data from a given computer of a given architecture is converted into software to be executed on another computer with a different type of architecture. This is accomplished by a target source software holding section holding the source code to be converted. Then a program data conversion processing section sequentially converts the software program from a starting address to an address in which a branch instruction is contained. The main software is held by a main software holding section. A conversion state registering section registers identification data showing if the program data to be converted is already converted for each corresponding address.

Abstract: A virtual computer system has a plurality of virtual computers and a virtual computer monitor for monitoring the virtual computers and for providing translation information describing the relationship between a virtual identification of the input/output apparatus structure to be recognized by the virtual computers and a physical identification to be actually used by the input/output apparatus structure. A hardware dynamically creates a subchannel necessary for performing an input/output process of the virtual computers and translation information when the virtual computer monitor provides the translation information to the hardware. The hardware translates the virtual identification to the physical identification based on the translation information when the virtual computer issues the input/output instruction, and for identifying the subchannel, thereby performing the input/output process.