Patents by Inventor Yasuhiko OGURA

Yasuhiko OGURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111320
    Abstract: Provided is a voltage regulator capable of suppressing a current consumption in a non-regulation state with a simple circuit configuration. The voltage regulator includes an output transistor supplying an output voltage based on a control voltage, an error amplifier circuit supplying an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage, a common source amplifier circuit supplying the control voltage to the output transistor based on the amplified signal, and a non-regulation state detection circuit supplying a detection signal to the common source amplifier circuit. The common source amplifier circuit includes a current control circuit including a plurality of parallel paths connecting between a control terminal of the output transistor and a power supply terminal, the plurality of parallel paths including a path to be closed in the non-regulation state and a path to be opened in the non-regulation state.
    Type: Application
    Filed: September 11, 2023
    Publication date: April 4, 2024
    Inventors: Atsushi HARUYAMA, Yasuhiko OGURA, Teruo SUZUKI
  • Patent number: 10915126
    Abstract: A voltage regulator includes an output voltage terminal which supplies an output voltage having a preset value, a voltage adjustment terminal which detects the output voltage, an error amplifier which compares the output voltage and a reference voltage to control the output voltage, a phase compensation capacitor, a test circuit which switches a normal mode with a test mode to test the phase compensation capacitor, a switch which makes the phase compensation capacitor valid or invalid, and a constant current source which makes a bias current of the error amplifier in the test mode lower than that in the normal mode.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: February 9, 2021
    Assignee: ABLIC INC.
    Inventors: Kaoru Sakaguchi, Yasuhiko Ogura, Munetaka Yoshimura, Hiroki Takahashi
  • Publication number: 20200073424
    Abstract: A voltage regulator includes an output voltage terminal which supplies an output voltage having a preset value, a voltage adjustment terminal which detects the output voltage, an error amplifier which compares the output voltage and a reference voltage to control the output voltage, a phase compensation capacitor, a test circuit which switches a normal mode with a test mode to test the phase compensation capacitor, a switch which makes the phase compensation capacitor valid or invalid, and a constant current source which makes a bias current of the error amplifier in the test mode lower than that in the normal mode.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 5, 2020
    Inventors: Kaoru Sakaguchi, Yasuhiko Ogura, Munetaka Yoshimura, Hiroki Takahashi
  • Patent number: 10496117
    Abstract: A voltage regulator includes an overshoot detection circuit which detects an overshoot based on an output voltage, an overshoot suppression circuit which controls a gate voltage of an output transistor based on a detection signal of the overshoot detection circuit, a state monitoring circuit which monitors a state of the voltage regulator, a timer circuit which operates the overshoot detection circuit for a preset period in response to a signal of the state monitoring circuit, and a timer off circuit which shortens the preset period counted by the timer circuit in response to the detection of the overshoot.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 3, 2019
    Assignee: ABLIC INC.
    Inventor: Yasuhiko Ogura
  • Publication number: 20190354126
    Abstract: A voltage regulator includes an overshoot detection circuit which detects an overshoot based on an output voltage, an overshoot suppression circuit which controls a gate voltage of an output transistor based on a detection signal of the overshoot detection circuit, a state monitoring circuit which monitors a state of the voltage regulator, a timer circuit which operates the overshoot detection circuit for a preset period in response to a signal of the state monitoring circuit, and a timer off circuit which shortens the preset period counted by the timer circuit in response to the detection of the overshoot.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 21, 2019
    Inventor: Yasuhiko OGURA
  • Patent number: 9864387
    Abstract: Provided is a voltage regulator which is not affected by a variation in output impedance of a reference voltage circuit, that is, which is configured to output voltage with a small change due to temperature. Two reference voltages respectively having positive and negative temperature coefficients are added together through transconductance amplifiers having large input impedances, respectively, and the resultant is amplified.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: January 9, 2018
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yasuhiko Ogura, Kaoru Sakaguchi
  • Publication number: 20170023960
    Abstract: Provided is a voltage regulator which is not affected by a variation in output impedance of a reference voltage circuit, that is, which is configured to output voltage with a small change due to temperature. Two reference voltages respectively having positive and negative temperature coefficients are added together through transconductance amplifiers having large input impedances, respectively, and the resultant is amplified.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 26, 2017
    Inventors: Yasuhiko OGURA, Kaoru SAKAGUCHI