Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.

Abstract: A semiconductor device includes, as a semiconductor region in which semiconductor layers are formed, an active region through which current flows and an edge termination structure region outside the active region and in which an edge termination structure is formed. The semiconductor device includes as the semiconductor layers: a drift layer of a first conductivity type and a base layer of a second conductivity type, in contact with the edge termination region; and includes an interlayer insulating film provided on the semiconductor region, on a side thereof where the base layer is formed. The edge termination region has a first semiconductor layer of the second conductivity type, continuous from the base layer and having an outer peripheral end not in contact with the interlayer insulating film, and a second semiconductor layer of the first conductivity type, in contact with the first semiconductor layer and forming a first PN junction therewith.

Abstract: An insulated-gate semiconductor device includes: an n+-type current spreading layer disposed on an n?-type drift layer; a p-type base region disposed on the current spreading layer; a n+-type main-electrode region arranged in an upper portion of the base region; an insulated-gate electrode structure provided in a trench; and a p+-type gate-bottom protection-region being in contact with a bottom of the trench, including a plurality of openings through which a part of the current spreading layer penetrates, being selectively buried in the current spreading layer, wherein positions of the openings cut on both sides of a central line of the trench are shifted from each other about the central line in a longitudinal direction of the trench in a planar pattern.

Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region includes a first portion that contains arsenic and a second portion that contains phosphorous.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.

Abstract: A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a first semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a third semiconductor layer of the second conductivity type in the active region and a third semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the third semiconductor layer, and the second semiconductor layer is not in contact with a surface of the first semiconductor layer.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.

Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.

Abstract: A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon carbide (SiC) substrate, forming a SiC layer on a front surface of the SiC substrate, selectively forming a first region in the SiC layer at a surface thereof, forming a source region and a contact region in the first region, forming a gate insulating film on the SiC layer and on a portion of the first region between the SiC layer and the source region, forming a gate electrode on the gate insulating film above the portion of the first region, forming an interlayer insulating film covering the gate electrode, forming a source electrode electrically connected to the source region and the contact region, forming a drain electrode on a back surface of the SiC substrate, forming a barrier film on and covering the interlayer insulating film, and forming a metal electrode on the source electrode and the barrier film.

Abstract: In a termination structure region, a first semiconductor layer of a first conductivity type, with an impurity concentration lower than that of a semiconductor substrate, is provided on the substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on a first side of the first semiconductor layer, opposite to a second side facing the substrate. Trenches penetrate the second semiconductor layer. At the first side in the first semiconductor layer, a first semiconductor region of the second conductivity type, with an impurity concentration higher than that of the second semiconductor layer, is provided at a side closer to an active region, contacting the second semiconductor layer. A second semiconductor region of the first conductivity type is provided in the second semiconductor layer, outside and adjacent to one of the trenches that is disposed at a farthest position from the active region.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.

Abstract: On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.

Abstract: A semiconductor device having a silicon carbide (SiC) substrate, a SiC layer formed on a front surface of the SiC substrate, a first region selectively formed in the SiC layer at a surface thereof, a source region and a contact region formed in the first region, a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region, a gate electrode disposed on the gate insulating film above the portion of the first region, an interlayer insulating film covering the gate electrode, a source electrode electrically connected to the source region and the contact region, a drain electrode formed on a back surface of the SiC substrate, a first barrier film formed on, and covering, the interlayer insulating film, and a metal electrode formed on the source electrode and the first barrier film.

Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.