Patents by Inventor Yasuhiko Tsukamoto

Yasuhiko Tsukamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8507327
    Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 13, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Tsukamoto, Kazuo Shimoyama
  • Publication number: 20110108883
    Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.
    Type: Application
    Filed: May 13, 2009
    Publication date: May 12, 2011
    Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventors: Yasuhiko Tsukamoto, Kazuo Shimoyama
  • Patent number: 5275707
    Abstract: A method of coating a metal article by forming a first electrodeposition coating layer having varistor properties on a metal article by an electrodeposition coating method by use of an electrodeposition coating film-forming composition containing from 7 to 50 parts by weight of an electrically semiconductive substance per 100 parts by weight of the solid content of the composition, and then forming a second electrodeposition coating layer on said first electrodeposition coating layer by an electrodeposition coating method by use of an anionic or cationic electrodeposition paint while applying a voltage exceeding the varistor voltage. The coating composition thus-produced has excellent varistor properties with superior corrosion resistance.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: January 4, 1994
    Assignee: Shinto Paint Co., Ltd.
    Inventors: Toshiyuki Yamada, Masaaki Nakashio, Yasuhiko Tsukamoto, Takeshi Kuninori