Abstract: A semiconductor device capable of implementing system configurations corresponding to various PCIe topologies is provided. A RAM stores one or more configuration registers that define function information of a PCIe device. A Link control unit decodes a request received from a PCIe host and outputs a decoded result to a CPU. The CPU reads a corresponding configuration register from the RAM based on the decoded result received from the Link control unit, and generates a response to the request and causes the Link control unit to transmit the response. Thus, system configurations corresponding to various PCIe topologies can be implemented.

Abstract: An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

Abstract: An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

Abstract: An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: A microcomputer includes an input terminal, coupled to the control terminal of a transmission gate, that receives a real-time request signal asserted by a peripheral. The transmission gate transfers data from a register to the peripheral in synchronism with the assertion of the real-time request signal so that data is provided to the peripheral in real time.

Abstract: To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

Abstract: In the region filling circuit of this invention, if only the starting position and the end position of the filling region rare supplied from outside, the inversion of bits in the filling area including the starting position and the end position where the whole bits are possibly not the subject of filling can be executed by hardware independently of a CPU, thereby to shorten the filling time and consequently reducing the time when the CPU is occupied during the filling.

Abstract: To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.