Abstract: A semiconductor device includes: an element isolation region in a semiconductor substrate; an active area in the semiconductor substrate; an interlayer insulation film on the element isolation region and the active area; an opening to which the element isolation region, the active area and a boundary therebetween are exposed; a glue layer in the opening; and a conductor on the glue layer. The element isolation region isolates the active area in the semiconductor substrate, and the active area overlaps a top surface of the isolation region.

Abstract: The present invention provides a structure in which a glue layer is formed on an active area and a shallow trench isolation with a glue layer interposed therebetween. A P-type silicon substrate includes the active area partitioned by the shallow trench isolation. An N+-type semiconductor region is formed in the active area. An interlayer insulation film is formed on the shallow trench isolation and active area, and has an opening to which the shallow trench isolation, active area, and a boundary between them are exposed. A glue layer is formed in the opening. Local interconnect wiring is formed in the opening and electrically connected to the N+-type semiconductor region through the glue layer. The active area overlaps the shallow trench isolation, and the glue layer has a portion opposed to the N+-type semiconductor region through the shallow trench isolation underlying the overlap of the active area.

Abstract: The present invention provides a structure in which a glue layer is formed on an active area and a shallow trench isolation with a glue layer interposed therebetween. A P-type silicon substrate includes the active area partitioned by the shallow trench isolation. An N+-type semiconductor region is formed in the active area. An interlayer insulation film is formed on the shallow trench isolation and active area, and has an opening to which the shallow trench isolation, active area, and a boundary between them are exposed. A glue layer is formed in the opening. Local interconnect wiring is formed in the opening and electrically connected to the N+-type semiconductor region through the glue layer. The active area overlaps the shallow trench isolation, and the glue layer has a portion opposed to the N+-type semiconductor region through the shallow trench isolation underlying the overlap of the active area.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.

Abstract: The present invention provides a structure in which a glue layer is formed on an active area and a shallow trench isolation with a glue layer interposed therebetween. A P-type silicon substrate includes the active area partitioned by the shallow trench isolation. An N+-type semiconductor region is formed in the active area. An interlayer insulation film is formed on the shallow trench isolation and active area, and has an opening to which the shallow trench isolation, active area, and a boundary between them are exposed. A glue layer is formed in the opening. Local interconnect wiring is formed in the opening and electrically connected to the N+-type semiconductor region through the glue layer. The active area overlaps the shallow trench isolation, and the glue layer has a portion opposed to the N+-type semiconductor region through the shallow trench isolation underlying the overlap of the active area.