Abstract: Decrease in a voltage supplied to a load caused by load fluctuations is minimized. A pulse frequency modulated signal generating unit 13 outputs a signal PFMOUT having a pulse frequency modulated according to a voltage supplied to the load 20. A pulse width modulated signal generating unit 14 outputs a signal PWMOUT having a pulse width modulated according to a voltage supplied to the load 20. In a state where the signal PFMOUT is selected, a selection unit 17 refers to a determination result of a frequency determining unit 15 and selects the signal PWMOUT as on/off signal for a semiconductor switch 11 when a low-level period in one cycle of the signal PFMOUT is not more than a predetermined time period. In a state where the signal PWMOUT is selected, the selection unit 17 selects the signal PFMOUT as on/off signal for the semiconductor switch 11 when a voltage determining unit 16 detects that a DC voltage (VOUT) at the load 20 exceeds a predetermined voltage.

Abstract: A boost DC-DC converter control circuit includes a transistor which is disposed between an input terminal and an output terminal of a boost DC-DC converter, and which is configured to interrupt an overcurrent between the two terminals. The control circuit includes an amplifier configured to amplify a difference between a voltage of the transistor on a side of the input terminal and a voltage of the transistor on a side of the output terminal, and a comparator configured to compare an output voltage from the amplifier with a predetermined reference voltage. On- and off-states of the transistor are controlled in response to an output voltage from the comparator.

Abstract: Decrease in a voltage supplied to a load caused by load fluctuations is minimized. A pulse frequency modulated signal generating unit 13 outputs a signal PFMOUT having a pulse frequency modulated according to a voltage supplied to the load 20. A pulse width modulated signal generating unit 14 outputs a signal PWMOUT having a pulse width modulated according to a voltage supplied to the load 20. In a state where the signal PFMOUT is selected, a selection unit 17 refers to a determination result of a frequency determining unit 15 and selects the signal PWMOUT as on/off signal for a semiconductor switch 11 when a low-level period in one cycle of the signal PFMOUT is not more than a predetermined time period. In a state where the signal PWMOUT is selected, the selection unit 17 selects the signal PFMOUT as on/off signal for the semiconductor switch 11 when a voltage determining unit 16 detects that a DC voltage (VOUT) at the load 20 exceeds a predetermined voltage.

Abstract: A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.

Abstract: A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.

Abstract: There is obtained a method of manufacturing a semiconductor device capable of preventing deterioration in electrical characteristic thereof. The method includes a step of forming the step section on the main surface of the semiconductor substrate and a step of forming the oxide film on the main surface of the semiconductor substrate using an active oxygen.