Patents by Inventor Yasuhiro Hirokane

Yasuhiro Hirokane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8456455
    Abstract: A display driving device is provided which drives a display panel having source lines provided for columns of pixels and which includes: first switches sw1 provided for the source lines; second switches sw2 provided for the source lines; AMP units 52 which are provided for the source lines and drive a pixel signal to the source lines via the second switches; an external power source 48 applying an intermediate voltage of the pixel signal to an intermediate voltage line, the intermediate voltage having a level between a minimum voltage level and a maximum voltage level of the pixel signal; and a control circuit 47 controlling turning on and off the first switches and the second switches, wherein the control unit temporarily turns off at least part of the second switches, and concurrently, temporarily turns on corresponding ones of the first switches during a transition period of the pixel signal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 4, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Kojima, Munehiko Ogawa, Yasuhiro Hirokane, Kazuyoshi Nishi
  • Publication number: 20100220080
    Abstract: A display driving device is provided which drives a display panel having source lines provided for columns of pixels and which includes: first switches sw1 provided for the source lines; second switches sw2 provided for the source lines; AMP units 52 which are provided for the source lines and drive a pixel signal to the source lines via the second switches; an external power source 48 applying an intermediate voltage of the pixel signal to an intermediate voltage line, the intermediate voltage having a level between a minimum voltage level and a maximum voltage level of the pixel signal; and a control circuit 47 controlling turning on and off the first switches and the second switches, wherein the control unit temporarily turns off at least part of the second switches, and concurrently, temporarily turns on corresponding ones of the first switches during a transition period of the pixel signal.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 2, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Kojima, Munehiko Ogawa, Yasuhiro Hirokane, Kazuyoshi Nishi
  • Patent number: 7365594
    Abstract: A current driver includes a gate line having a first and second nodes, K driving transistors, a terminal and a voltage generation section. The terminal receives a first current. The voltage generation section generates a bias voltage according to a current value of the first current. The gate line receives, at one of the first and second nodes, the bias voltage generated by the voltage generation section. Gates of the K transistors are connected between the first and second nodes of the gate line. In the voltage generation section, the relationship between the first current and the bias voltage is adjusted in the first mode, according to a current value of an output current flowing in a first driving transistor of the K driving transistors, and in the second mode, according to a current value of an output current flowing in a second driving transistor of the K driving transistors.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: April 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Kojima, Tetsuro Omori, Makoto Mizuki, Yasuhiro Hirokane, Hiroshi Kondo
  • Publication number: 20060139065
    Abstract: A current driver includes a gate line having a first and second nodes, K driving transistors, a terminal and a voltage generation section. The terminal receives a first current. The voltage generation section generates a bias voltage according to a current value of the first current. The gate line receives, at one of the first and second nodes, the bias voltage generated by the voltage generation section. Gates of the K transistors are connected between the first and second nodes of the gate line. In the voltage generation section, the relationship between the first current and the bias voltage is adjusted in the first mode, according to a current value of an output current flowing in a first driving transistor of the K driving transistors, and in the second mode, according to a current value of an output current flowing in a second driving transistor of the K driving transistors.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 29, 2006
    Inventors: Hiroshi Kojima, Tetsuro Omori, Makoto Mizuki, Yasuhiro Hirokane, Hiroshi Kondo