Patents by Inventor Yasuhiro Iida
Yasuhiro Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8238459Abstract: A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.Type: GrantFiled: January 28, 2009Date of Patent: August 7, 2012Assignee: Sony CorporationInventors: Takashi Yokokawa, Yasuhiro Iida, Toshiyuki Miyauchi, Takashi Hagiwara, Takanori Minamino, Naoya Haneda
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Publication number: 20120076587Abstract: The present invention provides a movable breakwater that can do with a small amount of compressed air supplied to raise the buoyant steel pipe. The buoyant steel pipe 6 includes a buoyancy tank 6d in which gas is filled, an air chamber 6e provided above the buoyancy tank 6d, a penetration pipe 19 that penetrates through the buoyancy tank 6d and feeds compressed air supplied from a pressure accumulator tank 13 to the air chamber 6e, and an open chamber 6f, whose top side is open, provided above the air chamber 6e and in the buoyant steel pipe 6 at the upper end portion thereof.Type: ApplicationFiled: June 4, 2010Publication date: March 29, 2012Applicant: MITSUBHISH HEAVY INDUSTRIES BRIDGE & STEEL STRUCTURES ENGINEERING CO., LTDInventors: Hirofumi Inagaki, Yasuhiro Iida, Keiji Kanai, Makoto Kobayashi, Akira Sakaguchi, Taro Arikawa, Hirohide Kimura, Hisanobu Nagatomo, Kazuyoshi Kihara
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Patent number: 8139664Abstract: Disclosed herein is a reception apparatus, including, an orthogonal frequency division multiplexing signal reception section, a first filter section, a subtraction section, a second filter section, a coefficient production section, and a Fast Fourier Transformation mathematic operation section.Type: GrantFiled: November 26, 2008Date of Patent: March 20, 2012Assignee: Sony CorporationInventors: Hidetoshi Kawauchi, Takashi Yokokawa, Takashi Horiguti, Naoki Yoshimochi, Hiroyuki Kamata, Ryoji Ikegaya, Yasuhiro Iida
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Patent number: 8081027Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.Type: GrantFiled: November 28, 2007Date of Patent: December 20, 2011Assignee: Sony CorporationInventors: Yasuhiro Iida, Kazuhisa Funamoto
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Patent number: 8078127Abstract: A reception device includes: an AGC circuit adapted to control the amplitude of a receive signal; a correction circuit adapted to correct the flutter component in the output signal of the AGC circuit; a synchronization circuit adapted to establish synchronization with the signal whose flutter component has been corrected by the correction circuit; and an equalization circuit adapted to perform an equalization process based on the signal with which synchronization has been established by the synchronization circuit and output the equalized signal, wherein the correction circuit includes a detection circuit, an IIR filter, a gain circuit, a flutter component correction circuit, and a gain control circuit.Type: GrantFiled: December 22, 2008Date of Patent: December 13, 2011Assignee: Sony CorporationInventors: Takanori Minamino, Yasuhiro Iida, Ryo Hasegawa
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Patent number: 7986615Abstract: A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.Type: GrantFiled: March 13, 2009Date of Patent: July 26, 2011Assignee: Sony CorporationInventors: Hidetoshi Kawauchi, Toshiyuki Miyauchi, Takashi Yokokawa, Takashi Horiguti, Naoki Yoshimochi, Yasuhiro Iida, Satoru Hori
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Publication number: 20110140007Abstract: To project a rectangular laser spot having a predetermined size and a high laser power density onto the surface of an object, a semiconductor manufacturing apparatus comprises a control unit for controlling power of a laser light source, an optical waveguide unit (1) including a core section (10) transmitting laser light and a clad section (11) covering the core section (10), and a lens (3) for forming the laser light output through the optical waveguide unit (1) into a laser spot having a predetermined shape, an output end surface (15) of the core section (10) has a rectangular shape with one side length of 1 ?m to 20 ?m and the other side length of 1 mm to 60 mm, and the laser source is set to make the power density of the laser spot output from the core section (10) to be 0.1 mW/?m2 or more.Type: ApplicationFiled: September 29, 2008Publication date: June 16, 2011Applicant: HITACHI COMPUTER PERIPHERALS CO., LTD.Inventors: Yoshiaki Ogino, Katsumi Kimura, Yasuhiro Iida, Kazuhiro Soga
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Patent number: 7773636Abstract: An information processing apparatus that processes a multiplexed stream including a frame having multiple slots, which is obtained by multiplexing multiple streams containing time information describing times is disclosed. The apparatus includes extracting means for extracting predetermined one or more slots from the frame of the multiplexed stream, storage means for storing data of the slot(s), and frequency dividing means for generating a second clock signal by frequency-dividing a first clock signal by a frequency division ratio N:M based on the number of clocks N corresponding to the time for one frame in the multiplexed stream and the number of clocks M for reading the data of the slot(s) extracted from the one frame from the storage means in the time for the one frame. The data of the slot or slots stored in the storage means is read in synchronization with the second clock signal.Type: GrantFiled: December 12, 2007Date of Patent: August 10, 2010Assignee: Sony CorporationInventor: Yasuhiro Iida
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Publication number: 20090231994Abstract: Disclosed herein is A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.Type: ApplicationFiled: March 13, 2009Publication date: September 17, 2009Inventors: Hidetoshi KAWAUCHI, Toshiyuki MIYAUCHI, Takashi YOKOKAWA, Takashi HORIGUTI, Naoki YOSHIMOCHI, Yasuhiro IIDA, Satoru HORI
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Publication number: 20090190695Abstract: Disclosed herein is a decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device including, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data, and decode second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data, and a synchronization detector configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data, the synchronization detector selecting and outputting one of the first decoded data and the second decoded data based on a result of the detection of the boundary.Type: ApplicationFiled: January 28, 2009Publication date: July 30, 2009Inventors: Takashi Yokokawa, Yasuhiro Iida, Toshiyuki Miyauchi, Takashi Hagiwara, Takanori Minamino, Naoya Haneda
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Publication number: 20090173724Abstract: Provided are a laser irradiation device and a laser irradiation method, which are suitable for a liquid crystal display device. The laser irradiation device comprises a semiconductor laser element group (1A) having a plurality of semiconductor laser elements (1) arranged therein for emitting laser beams of a wavelength of 370 nm to 480 nm, optical fibers (2) for transmitting the laser beams emitted from the semiconductor laser elements (1), a straight bundle (3) for holding the optical fibers (2) straight, an optical adjustor (4) for shaping the laser beams outputted from the optical fibers held by the straight bundle (3), into a linear shape and for smoothing the top of the laser intensity distribution thereby to output the smoothed laser beams, and an objective lens (5) for condensing the laser beams outputted from the optical adjustor (4), as a linear laser spot on an object The semiconductor laser element group (1A) has a total irradiation output value of 6 W to 100 W.Type: ApplicationFiled: March 16, 2007Publication date: July 9, 2009Inventors: Yoshiaki Ogino, Katsumi Kimura, Yasuhiro Iida
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Publication number: 20090163164Abstract: A reception device includes: an AGC circuit adapted to control the amplitude of a receive signal; a correction circuit adapted to correct the flutter component in the output signal of the AGC circuit; a synchronization circuit adapted to establish synchronization with the signal whose flutter component has been corrected by the correction circuit; and an equalization circuit adapted to perform an equalization process based on the signal with which synchronization has been established by the synchronization circuit and output the equalized signal, wherein the correction circuit includes a detection circuit, an IIR filter, a gain circuit, a flutter component correction circuit, and a gain control circuit.Type: ApplicationFiled: December 22, 2008Publication date: June 25, 2009Inventors: Takanori MINAMINO, Yasuhiro Iida, Ryo Hasegawa
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Publication number: 20090135931Abstract: Disclosed herein is a reception apparatus, including, an orthogonal frequency division multiplexing signal reception section, a first filter section, a subtraction section, a second filter section, a coefficient production section, and a Fast Fourier Transformation mathematic operation section.Type: ApplicationFiled: November 26, 2008Publication date: May 28, 2009Inventors: Hidetoshi KAWAUCHI, Takashi YOKOKAWA, Takashi HORIGUTI, Naoki YOSHIMOCHI, Hiroyuki KAMATA, Ryoji IKEGAYA, Yasuhiro IIDA
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Publication number: 20080159338Abstract: An information processing apparatus that processes a multiplexed stream including a frame having multiple slots, which is obtained by multiplexing multiple streams containing time information describing times is disclosed. The apparatus includes extracting means for extracting predetermined one or more slots from the frame of the multiplexed stream, storage means for storing data of the slot (s), and frequency dividing means for generating a second clock signal by frequency-dividing a first clock signal by a frequency division ratio N:M based on the number of clocks N corresponding to the time for one frame in the multiplexed stream and the number of clocks M for reading the data of the slot(s) extracted from the one frame from the storage means in the time for the one frame. The data of the slot or slots stored in the storage means is read in synchronization with the second clock signal.Type: ApplicationFiled: December 12, 2007Publication date: July 3, 2008Inventor: Yasuhiro Iida
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Patent number: 7388525Abstract: The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoder 181 performs SISO decoding on a signal supplied from a PR-SISO decoder 81 by using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding table 201 of a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decoder 84 via a deinterleaver 83. The turbo decoder 84 performs turbo decoding on the signal output from the 17PP-SISO decoder 181. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.Type: GrantFiled: July 5, 2004Date of Patent: June 17, 2008Assignee: Sony CorporationInventors: Toshiyuki Miyauchi, Yasuhiro Iida, Yuji Shinohara
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Publication number: 20080136510Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.Type: ApplicationFiled: November 28, 2007Publication date: June 12, 2008Inventors: Yasuhiro IIDA, Kazuhisa Funamoto
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Patent number: 7318186Abstract: The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P×P unit matrix, a quasi-unit matrix in which one or more 1s, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P×P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices.Type: GrantFiled: April 19, 2004Date of Patent: January 8, 2008Assignee: Sony CorporationInventors: Takahsi Yokokawa, Makiko Kan, Yasuhiro Iida, Atsushi Kikuchi
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Patent number: 7299397Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.Type: GrantFiled: April 19, 2004Date of Patent: November 20, 2007Assignee: Sony CorporationInventors: Takashi Yokokawa, Toshiyuki Miyauchi, Yasuhiro Iida
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Patent number: 7253299Abstract: A process for purifying N2-(1(S)-ethoxycarbonyl-3-phenylpropyl)-N6-trifluoroacetyl-L-lysine which comprises subjecting N2-(1(S)-ethoxycarbonyl-3-phenylpropyl)-N6-trifluoroacetyl-L-lysine contaminated with impurities to crystallization from a solvent comprising a water-soluble non-protic organic solvent, thereby removing the impurities into the mother liquor and giving crystals of N2-(1(S)-ethoxycarbonyl-3-phenylpropyl)-N6-trifluoroacetyl-L-lysine, according to which N2-(1(S)-ethoxycarbonyl-3-phenylpropyl)-N6-trifluoroacetyl-L-lysine having a high quality can be obtained in a high yield and a high productivity and which is suitable for practice on an industrial scale.Type: GrantFiled: July 10, 2002Date of Patent: August 7, 2007Assignee: Kaneka CorporationInventors: Yasuhiro Iida, Hajime Manabe, Yasuyoshi Ueda
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Patent number: 7246296Abstract: The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.Type: GrantFiled: October 8, 2003Date of Patent: July 17, 2007Assignee: Sony CorporationInventors: Takashi Yokokawa, Toshiyuki Miyauchi, Yasuhiro Iida, Kohei Yamamoto, Masayuki Hattori