Patents by Inventor Yasuhiro Ishii

Yasuhiro Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020029325
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: January 8, 1999
    Publication date: March 7, 2002
    Inventors: HIDEKI MURAYAMA, KAZUO HORIKAWA, HIROSHI YASHIRO, MASAHIKO YAMAUCHI, YASUHIRO ISHII, DAISUKE SASAKI
  • Patent number: 6197111
    Abstract: A heat shield for a crystal puller including an inner and an outer reflector. The inner and outer reflectors are spaced from each other an have reduced surface area in which they contact each other. Improved heat shielding of a growing crystal ingot reduces defects and permits a greater throughput of ingots produced by the crystal puller.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: March 6, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Lee Ferry, Yasuhiro Ishii
  • Patent number: 6148415
    Abstract: One or more combinations of an operating data processing machine and a backup data processing machine are connected together to enable backup switching wherein the backup machine takes over the data processing from the operating machine when a failure occurs in the operating machine. In particular, each of the operating and backup machines is connected to one or several system resources, such as data storage or data output devices. The operating processor exclusively occupies the system resources, and when a failure occurs the operating processor is disconnected therefrom. A disconnection completion notice is sent to the backup processor, which then begins to exclusively occupy the system resources for performing ongoing data processing that would have been performed by the operating processor had the failure not occurred. When a failure occurs with the operating processor, the data being processed and the data concerning the failure are dumped to an auxiliary memory to facilitate analysis of the failure.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: November 14, 2000
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Atuo Kobayashi, Yasuhiro Ishii
  • Patent number: 6049221
    Abstract: A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: April 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Ishibashi, Takehisa Hayashi, Tsutomu Goto, Hideki Murayama, Akira Yamagiwa, Yasuhiro Ishii, Naoki Hamanaka, Masabumi Shibata
  • Patent number: 6011791
    Abstract: In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: January 4, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata, Youichi Tanaka, Yasuhiro Ishii
  • Patent number: 5678062
    Abstract: A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuhiko Okada, Hideki Murayama, Takehisa Hayashi, Atsushi Ugajin, Yasuhiro Ishii, Masahiro Kitano
  • Patent number: 5602545
    Abstract: The carry-line comprises a plurality of MOSFETs connected in series. MOSFETs precharge each node when they receive precharge signals /PR. In the case of high-order priority designated mode, when input signals are given for turning on MOSFETs located between one end of the high-order bit side of the carry-line, the control circuit discharges the intermediate node separately from the carry-line. In the case of low-order bit priority designated mode, when input signals are given for turning on MOSFETs located between one end of the low-order bit side of the carry-line and the intermediate node, the control circuit discharges the intermediate node separately from the carry-line.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 11, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Ishii, Shigeharu Nakata
  • Patent number: 5420817
    Abstract: The same bit lines are used in common to a fixed data cell array and a memory cell array. The output section of the fixed data cell array is connected to an output circuit, just like the output section of the memory cell array. In response to signal CON supplied from a computer, an array selector examines the states of the arrays and performs switching between the state where one of the arrays can be selected and the state where neither of them can be selected. In the case where an externally-programmable memory, such as an EPROM, is employed, a write control circuit operates with respect only to the memory cell array, and prohibits data from being written in the fixed data cell array. The fixed data cell array is pre-programmed as a nonvolatile memory by programming means different from that used for programming the cells of the memory cell array.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: May 30, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Kitagawa, Shigeharu Nakata, Yasuhiro Ishii, Masue Shiba
  • Patent number: 5402239
    Abstract: Disclosed is a method of measuring the OF width of a cylindrical single crystal ingot using an optical non-contact type displacement measuring device. This method can avoid the labor and measurement errors as generally seen in the conventional manual method and provide an easy and precise measurement. Further, the method can be automated if necessary. This method comprises the steps of detecting the boundary points between the OF and the round surface of the single crystal ingot from the displacement to be obtained by scanning the sensor while detecting the distance between the sensor and the ingot surface including the OF, and calculating the OF width C from the scanning distance A of the sensor from the first boundary point detection position to the second boundary point detection position and the difference B between the first distance 1.sub.1 from the first boundary point to the sensor and the second distance 1.sub.2 from the sensor to the second boundary point.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: March 28, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yasuhiro Ishii, Yoshihiro Hirano
  • Patent number: 5363364
    Abstract: A disc recording/reproducing apparatus according to the present invention intermittently records and reproduces compressed digital audio data in normal recording/reproduction. In high-speed dubbing of digital audio data, two of such apparatuses are used, wherein compressed digital audio data is continuously reproduced from a disc for reproduction by the reproduction side apparatus to be directly applied to the recording side apparatus and continuously recorded on a disc for recording. Thus, the compressed high-speed dubbing of the digital audio data can be achieved without increasing a rotation speed of the disc even in high-speed dubbing.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: November 8, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kenji Torazawa, Yasuhiro Ishii, Tateo Toyama, Shin'ichiro Tomisawa, Nagatoshi Sugihara
  • Patent number: 5235641
    Abstract: In an information processing system having an upper rank apparatus and an external storage device which performs transmission and reception of data between the storage device and the upper rank apparatus, at least one of encryption and decryption of the data by use of an algorithm controlled by a desired data key is performed in the external storage device, while generation, encryption and decryption of the data key are performed on the upper rank apparatus side. By this configuration, the burden of the upper rank apparatus is largely reduced and the secrecy of data stored in the external storage device can be surely kept without spoiling the throughput of the whole system.
    Type: Grant
    Filed: March 12, 1991
    Date of Patent: August 10, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masafumi Nozawa, Akinobu Shimada, Toshifumi Nishimura, Katsuharu Kakuse, Tokuhiro Tsukiyama, Kiyoshi Yata, Yasuhiro Ishii, Kazuo Takaragi, Yasushi Kuba, Fujio Fujita
  • Patent number: 5225994
    Abstract: A novel and improved control and supervisory system for power distribution equipment including a plurality of terminal control and/or supervisory devices each capable of controlling and/or supervising a plurality of power distribution devices in an extremely simple, high-speed and efficient manner without requiring any central control and/or supervisory unit. To such control and/or supervisory operation, no vast and full knowledge of permitted and inhibited operations of varying kinds of power distribution devices connected therewith, as well as of the control and supervisory procedures therefor, is required.
    Type: Grant
    Filed: March 6, 1990
    Date of Patent: July 6, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ichiro Arinobu, Hirohisa Mizuhara, Yasuhiro Ishii, Katsuya Sakai, Hiromitsu Takahashi
  • Patent number: 5223752
    Abstract: A level conversion circuit includes first to nth circuits, each having an input terminal and first to nth output terminals where n is an integer, and first to nth signal lines coupled to the first to nth circuits. Each of the first to nth circuits comprises a part for outputting a first voltage to the first output terminal and outputting a second voltage to the second to nth output terminals other than the first output terminal when an input signal applied to the input terminal is at a first level and for maintaining the first to nth output terminals in high-impedance states when the input signal is at a second level different from the first level. The first output terminal of each of the first to nth circuits is connected to one of the first to nth signal lines so that first output terminals of the first to nth circuits are connected to mutually different signal lines.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: June 29, 1993
    Assignee: Fujitsu Limited
    Inventor: Yasuhiro Ishii
  • Patent number: 5144665
    Abstract: A cryptographic communication method and system for performing cryptographic communication between a host computer and a given one of plural terminals connected to the host computer by way of a communication network by using a data key designated by the given terminal or the host, wherein the host computer includes a cryptographic processing unit which includes a processing part for performing a public key cryptographic processing by using a pair of a public key and a private key and a common key cryptographic processing by using a common key, and an internal memory for storing master common key and master private key, a storage for recording as user private key information those data that result from the public key cryptographic processing performed by using a master public key on a plurality of user private keys which are in paired relation to user public keys held in the user terminals, respectively, and control means for performing input/output control between the storage and the cryptographic processing
    Type: Grant
    Filed: February 21, 1991
    Date of Patent: September 1, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takaragi, Yasuhiro Ishii, Tsutomu Nakamura
  • Patent number: 5058201
    Abstract: A mobile telecommuncations system has multiple base stations each defining a miniature service zone and capable of communicating with mobile stations present in the service zone over a radio link. Geographically associated ones of the base stations are spaced apart from each other by an area which is not responsive to electromagnetic waves on the radio links, whereby the base stations are allowed to share the same frequency for the electromagnetic waves. The base stations are interconnected to an on-road vehicle telecommunications network which switches communications to the base stations.
    Type: Grant
    Filed: May 24, 1989
    Date of Patent: October 15, 1991
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasuhiro Ishii, Tetsuji Isogai, Tatsuhiko Okazaki, Fumikazu Sato, Hiroto Yoneyama, Yukio Inotsume, Toshiyuki Kodama
  • Patent number: 4958094
    Abstract: In an emitter follower circuit including an emitter follower transistor (Q3, Q4), and a series-connected circuit connected to the emitter of the emitter follower transistor and including a current source (Q3, Q4) and a current source resistor, the current source resistor being formed by a MOS transistor (N4, N5), the emitter follower circuit being switched to active and inactive states by switching the state of the MOS transistor (N4, N5) by a control signal, there is provided current path means provided between the source and drain of the MOS transistor, for providing a resistance considerably larger than a resistance of the MOS transistor provided during conducting when the MOS transistor is at least cut off and passing an extremely small current passes therethrough at that time.
    Type: Grant
    Filed: June 28, 1989
    Date of Patent: September 18, 1990
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Ishii, Isao Fukushi
  • Patent number: 4428996
    Abstract: A diaphragm for a speaker formed of a mixture of carbon fiber, pulp and polyvinyl alcohol fiber as a binder with a thermosetting resin on the diaphragm base on which a metal film is provided in the interstices between fibers and on the entire fiber surface.
    Type: Grant
    Filed: June 24, 1981
    Date of Patent: January 31, 1984
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Yasushi Miyoshi, Yasuhiro Ishii
  • Patent number: 4308094
    Abstract: A diaphragm for a speaker obtained by forming a diaphragm base by screen processing a mixture of carbon fiber, pulp and polyvinyl alcohol fiber as a binder in a manner similar to that employed for making paper, depositing a thermosetting resin on the diaphragm base by impregnation or coating, and subjecting the diaphragm base, on which the thermosetting resin has been deposited, to electroless plating to deposit a metal film in the interstices between fibers and on the entire fiber surface.
    Type: Grant
    Filed: September 24, 1980
    Date of Patent: December 29, 1981
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasushi Miyoshi, Yasuhiro Ishii
  • Patent number: D403271
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: December 29, 1998
    Assignee: YKK Corporation
    Inventors: Yasuhiro Ishii, Atsushi Arai
  • Patent number: D423986
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: May 2, 2000
    Assignee: YKK Corporation
    Inventors: Yasuhiro Ishii, Atsushi Arai