Patents by Inventor Yasuhiro Ishiyama
Yasuhiro Ishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11377155Abstract: Included are a cowl top arranged on a lower end part of a front windshield; a dash panel provided with a first air intake port for sucking external air under and behind the cowl top, and on one side of the cowl top in a vehicle width direction; a hood arranged in front of the dash panel, and above an engine room; left and right fenders arranged respectively on sides of the cowl top; and left and right cowl sides extending in up-down and front-rear directions respectively on the opposite sides of the cowl top in the vehicle width direction. The right cowl side includes a second air intake port for introducing the external air to under the cowl top. The hood is arranged above the second air intake port. The right fender is arranged outside the second air intake port in the vehicle width direction.Type: GrantFiled: March 26, 2020Date of Patent: July 5, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Yasuhiro Ishiyama, Hiroyo Miyanaga
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Publication number: 20200307711Abstract: Included are a cowl top arranged on a lower end part of a front windshield; a dash panel provided with a first air intake port for sucking external air under and behind the cowl top, and on one side of the cowl top in a vehicle width direction; a hood arranged in front of the dash panel, and above an engine room; left and right fenders arranged respectively on sides of the cowl top; and left and right cowl sides extending in up-down and front-rear directions respectively on the opposite sides of the cowl top in the vehicle width direction. The right cowl side includes a second air intake port for introducing the external air to under the cowl top. The hood is arranged above the second air intake port. The right fender is arranged outside the second air intake port in the vehicle width direction.Type: ApplicationFiled: March 26, 2020Publication date: October 1, 2020Inventors: Yasuhiro ISHIYAMA, Hiroyo MIYANAGA
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Patent number: 8752491Abstract: A sewing machine is disclosed that includes a needle bar allowing attachment of a sewing needle including a needle eye to a lower end of thereof; a needle-bar lifting/lowering mechanism that moves the needle bar up and down; a presser foot; a presser foot lifting/lowering mechanism that moves the presser foot up and down; a hook that is provided with a beak for seizing a needle thread loop formed at the needle eye and that rotates in coordination with the up and down movement of the needle bar; and a controller that controls the presser foot lifting/lowering mechanism so as to resize a needle thread loop by lifting the presser foot to a predetermined height in coordination with a swing position of the needle bar and a predetermined height of the needle bar where the beak meets the needle thread loop.Type: GrantFiled: February 17, 2011Date of Patent: June 17, 2014Assignee: Brother Kogyo Kabushiki KaishaInventors: Masahiko Nagai, Masaru Jimbo, Eiichi Hamajima, Toru Imaeda, Hiroshi Yamasaki, Daisuke Ueda, Yasuhiro Ishiyama
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Patent number: 8292446Abstract: An illumination device for a multineedle sewing machine includes an illuminating member which has a light source and located at a lateral side of a needle bar case and is disposed so as to open portions of needle bars and portions of needles, a light amount adjusting unit which adjusts an amount of light of the light source, and a control unit which controls the light amount adjusting unit with movement of the needle bar case by the needle bar case moving mechanism together with the illuminating member so that a predetermined illuminance is maintained at least in part of an illuminated area which is illuminated by the light source. The part of the illuminated area is located near the needle drop position.Type: GrantFiled: March 3, 2010Date of Patent: October 23, 2012Assignee: Brother Kogyo Kabushiki KaishaInventors: Shinya Fujihara, Yasuhiro Ishiyama, Nobuaki Matsumoto, Junnosuke Matsuda
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Publication number: 20110203505Abstract: A sewing machine is disclosed that includes a needle bar allowing attachment of a sewing needle including a needle eye to a lower end of thereof; a needle-bar lifting/lowering mechanism that moves the needle bar up and down; a presser foot; a presser foot lifting/lowering mechanism that moves the presser foot up and down; a hook that is provided with a beak for seizing a needle thread loop formed at the needle eye and that rotates in coordination with the up and down movement of the needle bar; and a controller that controls the presser foot lifting/lowering mechanism so as to resize a needle thread loop by lifting the presser foot to a predetermined height in coordination with a swing position of the needle bar and a predetermined height of the needle bar where the beak meets the needle thread loop.Type: ApplicationFiled: February 17, 2011Publication date: August 25, 2011Applicant: BROTHER KOGYO KABUSHIKI KAISHAInventors: Masahiko NAGAI, Masaru JIMBO, Eiichi HAMAJIMA, Toru IMAEDA, Hiroshi YAMASAKI, Daisuke UEDA, Yasuhiro ISHIYAMA
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Publication number: 20100242820Abstract: An illumination device for a multineedle sewing machine includes an illuminating member which has a light source and located at a lateral side of a needle bar case and is disposed so as to open portions of needle bars and portions of needles, a light amount adjusting unit which adjusts an amount of light of the light source, and a control unit which controls the light amount adjusting unit with movement of the needle bar case by the needle bar case moving mechanism together with the illuminating member so that a predetermined illuminance is maintained at least in part of an illuminated area which is illuminated by the light source. The part of the illuminated area is located near the needle drop position.Type: ApplicationFiled: March 3, 2010Publication date: September 30, 2010Applicant: BROTHER KOGYO KABUSHIKI KAISHAInventors: Shinya Fujihara, Yasuhiro Ishiyama, Nobuaki Matsumoto, Junnosuke Matsuda
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Patent number: 7272812Abstract: A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at the same time is provided. When a layout designing operation as to a semiconductor memory circuit and a semiconductor analog circuit is manually carried out in a semi-automatic designing manner, both the circuit designing operation and the layout designing operation can be carried out at the same time, so that a designing time period can be shortened.Type: GrantFiled: October 8, 2004Date of Patent: September 18, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuhiro Ishiyama
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Publication number: 20070200236Abstract: A semiconductor integrated circuit device includes: a semiconductor substrate; a semiconductor chip including a plurality of functional blocks formed independently from each other in predetermined regions of the semiconductor substrate and each including a pad for transmitting a signal; and a plurality of inter-pad interconnects being connected to the pads and being capable of being cut. Signal transmission between the respective functional blocks is performed through the respective inter-pad interconnects.Type: ApplicationFiled: January 10, 2007Publication date: August 30, 2007Inventor: Yasuhiro Ishiyama
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Patent number: 7250686Abstract: A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and is connected to the second internal circuit, at least one first connecting member for connecting between the second semiconductor chip provided on the first semiconductor chip, at least one first conductive pad and at least one second conductive pad, and at least one second connecting member led from at least one first conductive.Type: GrantFiled: April 28, 2006Date of Patent: July 31, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuhiro Ishiyama
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Patent number: 7117462Abstract: In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.Type: GrantFiled: September 28, 2001Date of Patent: October 3, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomoo Kimura, Tomonori Kataoka, Yoichi Nishida, Ikuo Fuchigami, Ken Kawai, Yasuhiro Ishiyama
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Publication number: 20060206297Abstract: There are provided a different part detecting portion for detecting the different part of the result of a simulation, a difference detecting portion for detecting a difference in the result of a simulation, an input different part display portion for displaying any of circuits having different simulation modes which has a difference, a different part display portion for displaying a circuit having a difference in the result of a simulation, a condition display portion for displaying, on a circuit diagram, an option to be used in a simulation, a record managing portion for managing the execution history of the result of a simulation, a condition checking portion for ascertaining whether or not a condition is accurately set in each circuit in the execution of a simulation, and a match checking portion for confirming the non-coincidence of the names and numbers of pins between the simulation modes.Type: ApplicationFiled: March 1, 2006Publication date: September 14, 2006Inventor: Yasuhiro Ishiyama
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Publication number: 20060197212Abstract: A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first. semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and is connected to the second internal circuit, at least one first connecting member for connecting between the second semiconductor chip provided on the first semiconductor chip, at least one first conductive pad and at least one second conductive pad, and at least one second connecting member led from at least one first conductive.Type: ApplicationFiled: April 28, 2006Publication date: September 7, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuhiro Ishiyama
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Publication number: 20050097495Abstract: A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at the same time is provided.Type: ApplicationFiled: October 8, 2004Publication date: May 5, 2005Inventor: Yasuhiro Ishiyama
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Publication number: 20040245651Abstract: A first inventive semiconductor device includes: a die pad 1; a mother chip 2; a daughter chip 3; a conductor film 7 formed on the back surface of the daughter chip 3; bumps 4; a lead 5; and a bonding wire 6, as shown in FIG. 1B. The conductor film 7 is connected to an external member via the bonding wire 6 and the lead 5, thus stabilizing a substrate potential. In addition, the conductor film 7 has a high heat conductivity and a low electrical resistance, thereby improving the heat radiation performance of the semiconductor device and suppressing noise radiation.Type: ApplicationFiled: June 9, 2003Publication date: December 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takashige Nishisako, Yasuhiro Ishiyama, Hisakazu Kotani
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Publication number: 20030155635Abstract: A semiconductor device of the present invention comprises a first semiconductor chip that includes a first internal circuit and at least one first conductive pad which is provided on its upper surface and is not connected to the first internal circuit, a second semiconductor chip provided on the first semiconductor chip that includes a second internal circuit and at least one second conductive pad which is provided on its upper surface and is connected to the second internal circuit, at least one first connecting member for connecting between the second semiconductor chip provided on the first semiconductor chip, at least one first conductive pad and at least one second conductive pad, and at least one second connecting member led from at least one first conductive.Type: ApplicationFiled: February 21, 2003Publication date: August 21, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuhiro Ishiyama
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Publication number: 20020040465Abstract: In a circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and in-put data representing waveforms with time of voltages or currents used for operation simulation, and expanding the circuit diagram data to a memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary volt-age/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.Type: ApplicationFiled: September 28, 2001Publication date: April 4, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tomoo Kimura, Tomonori Kataoka, Yoichi Nishida, Ikuo Fuchigami, Ken Kawai, Yasuhiro Ishiyama