Abstract: The input-output buffer circuit is provided with a PMOS transistor and an NMOS transistor which form an output driver which are ordinary MOS transistors instead of high breakdown voltage transistors. A resistor is inserted between drains of those MOS transistors and an external terminal. The resistance of this resistor is such that it generates a voltage drop as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be safely applied to those MOS transistors and to become a potential which is at least a threshold level of an input buffer, when a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed.

Abstract: The input-output buffer circuit is provided with a PMOS transistor and an NMOS transistor which form an output driver are determined to be ordinary MOS transistors instead of high breakdown voltage transistors. A resistor is inserted between drains of those MOS transistors and an external terminal. The resistance of this resistor is such that it generates a voltage drop as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be applied to those MOS transistors and to become a potential which is at least a threshold level of an input buffer, when a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed.

Abstract: A semiconductor recording device includes two transistors connected to two bit lines, respectively, that are turned OFF by a retention test signal during a retention test. One of the bit lines is put into high impedance with the help of a write driver, and “0” is output to the other bit line. Therefore, charge at H-level is not supplied to the bit lines during the retention test, so that a memory cell having a faulty connection will not temporarily retain H-level data.

Abstract: A clock signal generator having a pre-phase converter for generating in response to an input clock signal a plurality of pre-delay clock signals with different phases; and main phase converters each of which receives one of the pre-delay clock signals, and generates a plurality of main delay clock signals with their phases different from each other, thereby generating multiple main delay clock signals with their phases different from each other.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: A semiconductor storage device which can perform reading operations at a high speed is provided. A voltage apply control circuit (21) captures an ATD control signal(S7) of an ATD control circuit (7) and an output signal (OUT) of an output buffer (6) and outputs a control signal (S21) to a voltage apply circuit (22) on the basis of the output signal (OUT) during an H level period of the ATD control signal (S7). The voltage apply circuit (22) applies voltages to a bit line BL and a bit line BL so that the bit line pair BL and BL is equalized in a shorter period as possible on the basis of the control signal (S21). The equalizing processing is accomplished at a high speed, which enables high-speed reading operations.