Patents by Inventor Yasuhiro Kashiwazaki
Yasuhiro Kashiwazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951677Abstract: A three dimensional manufactured product is manufactured A speed of filing an uncured light curing resin in a space for a next layer is enhanced, to improve a manufacturing speed. One surface of a container housing a light curing resin is configured by a gas-permeable sheet that faces the light curing resin, and transmits irradiation light of a light irradiating apparatus, and a light transmitting plate disposed at an outer side of the container from the gas permeable member. A pressurizing chamber controllable in pressure by a pressure controlling apparatus is defined between the gas-permeable sheet and the light transmitting plate. At moving a manufacturing stage, an inside of the pressurizing chamber is de-pressurized to cause the gas-permeable sheet to perform concave surface deformation, and at a time of performing light irradiation, gas in the pressurizing chamber is caused to permeate into the light curing resin by pressurizing.Type: GrantFiled: April 28, 2021Date of Patent: April 9, 2024Assignee: Canon Kabushiki KaishaInventors: Takashi Arai, Yasuhiro Sekine, Akio Kashiwazaki, Toshiki Ito
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Patent number: 7885132Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: May 7, 2009Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Publication number: 20090213667Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: ApplicationFiled: May 7, 2009Publication date: August 27, 2009Applicant: Renesas Technology CorporationInventors: Takashi KUBO, Takashi ITOH, Yasuhiro KASHIWAZAKI, Taku OGURA, Kiyohiro FURUTANI
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Patent number: 7542363Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: March 18, 2005Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Publication number: 20050213387Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: ApplicationFiled: March 18, 2005Publication date: September 29, 2005Inventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Patent number: 6853592Abstract: A selector selects one standard voltage from among divided voltages from a voltage dividing circuit and a reference voltage from a reference voltage generating circuit, in accordance with a test mode enable signal and a reference voltage select signal. An internal voltage generating circuit receives the standard voltage from the selector and generates an internal power supply voltage.Type: GrantFiled: August 18, 2003Date of Patent: February 8, 2005Assignee: Renesas Technology Corp.Inventor: Yasuhiro Kashiwazaki
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Patent number: 6819618Abstract: A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with reference to the register, counts up an address while skipping an address requiring no refresh operation, to thereby generate an address of the memory space to be refreshed, and a refresh cycle generating circuit that with reference to the register 15, generates a refresh cycle with a cycle which varies according to the number of the memory space requiring the refresh operation.Type: GrantFiled: October 31, 2003Date of Patent: November 16, 2004Assignee: Renesas Technology Corp.Inventor: Yasuhiro Kashiwazaki
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Publication number: 20040170067Abstract: A selector selects one standard voltage from among divided voltages from a voltage dividing circuit and a reference voltage from a reference voltage generating circuit, in accordance with a test mode enable signal and a reference voltage select signal. An internal voltage generating circuit receives the standard voltage from the selector and generates an internal power supply voltage.Type: ApplicationFiled: August 18, 2003Publication date: September 2, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Yasuhiro Kashiwazaki
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Publication number: 20040165465Abstract: A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with reference to the register, counts up an address while skipping an address requiring no refresh operation, to thereby generate an address of the memory space to be refreshed, and a refresh cycle generating circuit that with reference to the register 15, generates a refresh cycle with a cycle which varies according to the number of the memory space requiring the refresh operation.Type: ApplicationFiled: October 31, 2003Publication date: August 26, 2004Applicant: Renesas Technology Corp.Inventor: Yasuhiro Kashiwazaki
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Patent number: 6724228Abstract: A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.Type: GrantFiled: February 7, 2003Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventor: Yasuhiro Kashiwazaki
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Patent number: 6721232Abstract: Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.Type: GrantFiled: June 18, 2002Date of Patent: April 13, 2004Assignee: Renesas Technology Corp.Inventor: Yasuhiro Kashiwazaki
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Publication number: 20040008064Abstract: A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.Type: ApplicationFiled: February 7, 2003Publication date: January 15, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Yasuhiro Kashiwazaki
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Publication number: 20030209790Abstract: A jumper circuit is provided for enabling the switching of the mode in the case that a bare chip is detected as being defective, wherein data that has been inputted to/outputted from a bare chip detected as being defective is inputted to/outputted from a good function chip for repair mounted on the rear surface of a module substrate so that the good function chip functions in place of the bare chip that has been detected as being defective. Thereby, a semiconductor memory module is obtained that can be repaired in the case that a bare chip is detected as being defective from among a plurality of bare chips while effectively utilizing bare chips other than the bare chip that has become defective from among the plurality of bare chips.Type: ApplicationFiled: September 16, 2002Publication date: November 13, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Matsumoto, Hiromi Okimoto, Yasuhiro Kashiwazaki
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Publication number: 20030202372Abstract: A good chip for repair is provided only in a position on the rear surface of a module substrate corresponding to the position of a bare chip that has been detected as being defective. In addition, the entirety of the rear surface of the module substrate is integrally molded regardless of whether or not a good chip is mounted. Thereby, a semiconductor memory module is formed so as to be in a form wherein gaps do not easily occur between a plurality of semiconductor memory modules when the semiconductor memory modules are packed in a box for transport of the semiconductor memory modules. As a result, damage can be prevented from occurring in a semiconductor module wherein good chips for repair are mounted at the time of transport in packaging.Type: ApplicationFiled: October 22, 2002Publication date: October 30, 2003Applicants: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Yasuhiro Kashiwazaki, Yoshio Fudeyasu, Tatsuji Kobayashi
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Publication number: 20030112697Abstract: Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.Type: ApplicationFiled: June 18, 2002Publication date: June 19, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Yasuhiro Kashiwazaki
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Patent number: 6570815Abstract: In a DLL circuit of a DDR SDRAM, in addition to a replica buffer for compensating delay in an output buffer, a replica buffer for compensating flight time is provided. The phase of a clock signal CLKP outputted to the outside so as to be locked with a clock signal BUFFCLK can be adjusted in accordance with a control signal b[1:0]. For a controller receiving data in a lump from a plurality of semiconductor memory devices, the arriving timings of data from the semiconductor memory devices can be aligned. Therefore, it is unnecessary to capture data in response to a data strobe signal DQS, so that burden on the controller is lessened.Type: GrantFiled: October 11, 2001Date of Patent: May 27, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yasuhiro Kashiwazaki
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Publication number: 20020159325Abstract: In a DLL circuit of a DDR SDRAM, in addition to a replica buffer for compensating delay in an output buffer, a replica buffer for compensating flight time is provided. The phase of a clock signal CLKP outputted to the outside so as to be locked with a clock signal BUFFCLK can be adjusted in accordance with a control signal b[1:0]. For a controller receiving data in a lump from a plurality of semiconductor memory devices, the arriving timings of data from the semiconductor memory devices can be aligned. Therefore, it is unnecessary to capture data in response to a data strobe signal DQS, so that burden on the controller is lessened.Type: ApplicationFiled: October 11, 2001Publication date: October 31, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Yasuhiro Kashiwazaki