Patents by Inventor Yasuhiro Kumagai

Yasuhiro Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210398860
    Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 23, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
  • Publication number: 20210020630
    Abstract: The present disclosure provides a high-voltage tolerant semiconductor element preventing performance deterioration caused by impurity diffusion. The high-voltage tolerant semiconductor element includes a source portion (S), a well impurity region (PW) disposed around the source portion (S), and at least two gate portions (G) disposed at two sides of the source portion (S). An impurity concentration of the well impurity region is higher than an impurity concentration of a silicon substrate. A space between the two gate portions (G) is greater than a diffusion length (DD) of impurities.
    Type: Application
    Filed: June 15, 2020
    Publication date: January 21, 2021
    Applicant: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventors: MASATOSHI TAYA, NORIO NAKANO, YASUHIRO KUMAGAI
  • Patent number: 9443808
    Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 13, 2016
    Assignee: SYNAPTICS DISPLAY DEVICES GK
    Inventors: Hisao Nakamura, Yuichi Nakagomi, Yasuhiro Kumagai
  • Patent number: 9269672
    Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.
    Type: Grant
    Filed: September 20, 2014
    Date of Patent: February 23, 2016
    Assignee: Synaptics Display Devices GK
    Inventors: Yasuhiro Kumagai, Masami Koketsu
  • Publication number: 20150108611
    Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.
    Type: Application
    Filed: September 20, 2014
    Publication date: April 23, 2015
    Inventors: Yasuhiro KUMAGAI, Masami KOKETSU
  • Publication number: 20150021733
    Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 22, 2015
    Inventors: Hisao Nakamura, Yuichi Nakagomi, Yasuhiro Kumagai