Abstract: An eyeglasses-type wearable device of an embodiment can handle various data inputs. The device includes right and left eye frames corresponding to positions of right and left eyes and nose pads corresponding to a position of a nose. Eye motion detection electrodes (sightline detection sensor electrodes) are provided with the nose pads to detect the eye motion of a user. Transmitter/receiver electrodes (capacitance sensor electrodes) of a gesture detector are provided with a part of the right and left eye frames to detect a gesture of the user. Various data inputs are achieved by a combination of input A corresponding to a gesture of the user detected by the gesture detector and input B corresponding to the eye motion of the user detected by the eye motion detector.

Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.

Abstract: The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.

Abstract: The present disclosure provides a high-voltage tolerant semiconductor element preventing performance deterioration caused by impurity diffusion. The high-voltage tolerant semiconductor element includes a source portion (S), a well impurity region (PW) disposed around the source portion (S), and at least two gate portions (G) disposed at two sides of the source portion (S). An impurity concentration of the well impurity region is higher than an impurity concentration of a silicon substrate. A space between the two gate portions (G) is greater than a diffusion length (DD) of impurities.

Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.

Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.

Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.

Abstract: A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring.