Abstract: A chimney arranged inside of a reactor pressure vessel of a natural-circulation boiling water reactor is provided. The chimney includes plural flow channels which guide a steam-water two-phase flow generated in a reactor core to the upper part of the reactor pressure vessel. Each of the flow channels is formed by plural flow channel separation walls whose lower-most part is supported by a chimney lattice plate. Chimney spacers that support a horizontal load are arranged between the flow channel separation walls of the adjacent flow channels. Chimney support rings that support the horizontal load are arranged at the outermost periphery of the plural flow channels that are supported by the chimney lattice plate.

Abstract: The present invention provides a chimney for a natural-circulation boiling water reactor having structural soundness capable of standing a horizontal load generated by a flow-induced vibration, an earthquake and the like.

Abstract: The object of the invention is to accurately evaluate integrity of vibration of a dryer of an actual system. The evaluating method for integrity of vibration of a steam dryer using a reduced model in a nuclear plant including the steam dryer for reducing moisture of steam generated inside a steam dome of a nuclear reactor pressure vessel, and a plurality of main steam pipes for transporting the steam to outside includes the steps of performing a steam test with the reduced model, calculating fluctuating stress applied to the steam dryer, and confirming integrity of vibration. According to the invention, it is possible to evaluate the pressure fluctuation of a dryer of an actual system more accurately.

Abstract: A testing apparatus is configured by using test facilitation circuits and a tester, and expectation data are output from the tester, whereby the pins of the tester corresponding to the output-dedicated terminals of DUTs can be shared by the DUTs. Even if the number of DUTs is increased to three or more, the existing pins of the tester corresponding to the output-dedicated terminals of the existing DUTs can still serve for the output-dedicated terminals of new DUTs. Therefore, to increase the simultaneous measurement number L, it is not necessary to increase the number of pins of the tester with the number K of output-dedicated terminals of each DUT as a proportionality constant.

Abstract: A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored the replacement information; and an input/output port for outputting information PI actually stored in the first LT fuse group and information CI actually stored in the second LT fuse group to an external memory tester. The first and second LT fuse groups are fabricated according to the same conditions, and the laser input to the respective group is set to be under the same conditions.

Abstract: A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored the replacement information; and an input/output port for outputting information PI actually stored in the first LT fuse group and information CI actually stored in the second LT fuse group to an external memory tester. The first and second LT fuse groups are fabricated according to the same conditions, and the laser input to the respective group is set to be under the same conditions.

Abstract: A low-cost semiconductor tester which saves memory space for storing a test pattern by means of producing a high-speed clock while preparing a test pattern at a low-speed test cycle and which has a test-pattern storage circuit of small storage capacity, as well as a semiconductor test method using the semiconductor tester. The semiconductor tester includes a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal, a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle, and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured. A ring oscillation circuit is provided in the waveform formation circuit and has a variable delay circuit. The ring oscillation circuit converts the output waveform, which waveform is produced at a predetermined timing, into a high-speed clock waveform.