Patents by Inventor Yasuhiro Motoyama
Yasuhiro Motoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8357933Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.Type: GrantFiled: July 20, 2010Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
-
Patent number: 8323992Abstract: The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.Type: GrantFiled: September 8, 2011Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Seigo Nakamura, Iwao Natori, Yasuhiro Motoyama
-
Patent number: 8206997Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.Type: GrantFiled: July 15, 2010Date of Patent: June 26, 2012Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
-
Publication number: 20120064646Abstract: The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.Type: ApplicationFiled: September 8, 2011Publication date: March 15, 2012Inventors: Seigo NAKAMURA, Iwao Natori, Yasuhiro Motoyama
-
Patent number: 8062911Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.Type: GrantFiled: December 17, 2007Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
-
Publication number: 20110175634Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Inventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
-
Publication number: 20110136272Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: February 1, 2011Publication date: June 9, 2011Inventors: Masayoshi OKAMOTO, Yoshiaki HASEGAWA, Yasuhiro MOTOYAMA, Hideyuki MATSUMOTO, Shingo YORISAKI, Akio HASEBE, Ryuji SHIBATA, Yasunori NARIZUKA, Akira YABUSHITA, Toshiyuki MAJIMA
-
Patent number: 7901958Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: GrantFiled: August 10, 2010Date of Patent: March 8, 2011Assignee: Renesas Electronics CorporationInventors: Masayoshi Okamoto, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
-
Publication number: 20100304510Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.Type: ApplicationFiled: August 10, 2010Publication date: December 2, 2010Inventors: Masayoshi OKAMOTO, Yoshiaki Hasegawa, Yasuhiro Motoyama, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Ryuji Shibata, Yasunori Narizuka, Akira Yabushita, Toshiyuki Majima
-
Publication number: 20100279502Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.Type: ApplicationFiled: July 15, 2010Publication date: November 4, 2010Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
-
Publication number: 20100277192Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.Type: ApplicationFiled: July 20, 2010Publication date: November 4, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Akio HASEBE, Hideyuki MATSUMOTO, Shingo YORISAKI, Yasuhiro MOTOYAMA, Masayoshi OKAMOTO, Yasunori NARIZUKA, Naoki OKAMOTO
-
Patent number: 7776626Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.Type: GrantFiled: March 11, 2005Date of Patent: August 17, 2010Assignee: Renesas Technology Corp.Inventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
-
Patent number: 7688086Abstract: To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.Type: GrantFiled: November 2, 2006Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Yasuhiro Motoyama, Yoshimi Horigome, Seigo Nakamura, Iwao Natori
-
Patent number: 7598100Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.Type: GrantFiled: November 18, 2004Date of Patent: October 6, 2009Assignee: Renesas Technology Corp.Inventors: Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka
-
Patent number: 7537943Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.Type: GrantFiled: October 2, 2007Date of Patent: May 26, 2009Assignee: Renesas Technology Corp.Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura
-
Publication number: 20090130785Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.Type: ApplicationFiled: November 18, 2004Publication date: May 21, 2009Inventors: Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka
-
Patent number: 7517707Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.Type: GrantFiled: April 12, 2007Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Masayoshi Okamoto, Hideyuki Matsumoto, Shingo Yorisaki, Akio Hasebe, Yasuhiro Motoyama, Akira Shimase
-
Publication number: 20090017565Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.Type: ApplicationFiled: March 11, 2005Publication date: January 15, 2009Inventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
-
Patent number: 7407823Abstract: During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and back surface thereof is prepared. An elastomer in the form of a sheet and a polyimide sheet are successively disposed on the main surface of the pressing tool. With th elastomer and the polyimide sheet being electrostatically attracted to the pressing tool, the pressing tool is disposed on a thin-film sheet such that the main surface thereof faces the back surface (the surface opposite to the main surface thereof formed with the probe) of the thin-film sheet. Then, the thin-film sheet with the pressing tool bonded thereto is attached to a probe card.Type: GrantFiled: June 21, 2006Date of Patent: August 5, 2008Assignee: Renesas Technology Corp.Inventors: Akio Hasebe, Masayoshi Okamoto, Yasunori Narizuka, Shingo Yorisaki, Yasuhiro Motoyama
-
Publication number: 20080160657Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami