Patents by Inventor Yasuhiro Moya

Yasuhiro Moya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6747319
    Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: June 8, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
  • Patent number: 6492692
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: December 10, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Patent number: 6469405
    Abstract: A constant-current FET functions as a constant current element by application of a constant voltage to the gate thereof. A first switch FET is disposed between the constant-current FET and a power supply without another switching element being disposed between the constant current FET and an output terminal. A second switch FET that performs an on/off operation in association with an on/off operation performed by the first switch FET is connected between the output terminal and ground.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: October 22, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo, Tadao Akamine
  • Patent number: 6359639
    Abstract: A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 19, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Tatsuya Kitta, Yoshihide Kanakubo, Yasuhiro Moya, Kazutoshi Ishii, Sumitaka Gotou
  • Patent number: 6346960
    Abstract: A thermal head driving integrated circuit may be used to perform an “n” color or “n” gradation printing operation with a simplified circuit having a reduced size by employing a single delay element connected to a plurality of resistive heating elements. The integrated circuit has a plurality of drive units each for driving a respective one of the heating elements and each having a drive transistor for driving a respective heating element, one or more delay elements, the number of delay elements being less than “n”, for supplying delayed print data to the drive transistor, a print data storing unit for storing the print data of each of the “n” types, and a print data supplying unit for supplying print data stored in the print data storing unit to the “n” delay elements.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: February 12, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshihide Kanakubo, Yasuhiro Moya, Tatsuya Kitta, Kazutoshi Ishii, Sumitaka Goto
  • Publication number: 20010009288
    Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
    Type: Application
    Filed: March 9, 2001
    Publication date: July 26, 2001
    Applicant: Seiko Instruments Inc.
    Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
  • Patent number: 6222235
    Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: April 24, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
  • Patent number: 6134136
    Abstract: Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: October 17, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Yoshihide Kanakubo, Tatuya Kitta
  • Patent number: 6107128
    Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: August 22, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo
  • Patent number: 6022792
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 8, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara