Patents by Inventor Yasuhiro Narikawa

Yasuhiro Narikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip-chip connecting method, flip-chip connected structure and electronic device using the same
    Patent number: 6153938
    Abstract: A stable low-connecting resistance connection arrangement having a high yield rate without using any special material or process for a substrate. A flip-chip connecting structure in which the semiconductor integrated circuit (IC) chip is mounted directly on an organic circuit substrate. To achieve reliable connection and low-connecting resistance, the present invention absorbs variation of the heights of projecting electrodes formed on a semiconductor IC chip and substrate electrodes of an organic circuit substrate for example, by deforming the substrate electrodes and/or substrate layer of the organic circuit substrate. Resin of a conductive paste disposed between the projecting electrodes and substrate electrodes is squeezed out leaving a high density conductive particle layer to lower a contact resistance between such electrodes.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: November 28, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Toyoki Asada, Yoshio Oozeki, Yasuo Amano, Kunio Matsumoto, Yasuhiro Narikawa