Abstract: A transmission device according to the present disclosure includes: a driver that transmits a transmission signal including two or more signals; an alternating current signal generator including a phase-locked loop circuit that generates an alternating current signal, the alternating current signal generator being configured to set a phase and frequency of the alternating current signal; an amplifier configured to amplify the alternating current signal generated by the alternating current signal generator and set amplitude of the alternating current signal; and a superimposer that superimposes the alternating current signal amplified by the amplifier on the two or more signals.

Abstract: A transmission device according to the present disclosure includes: a driver circuit that includes a plurality of output circuits each including a plurality of transistors, and outputs a plurality of output signals from the plurality of output circuits on a basis of a plurality of driver input signals being respectively inputted to the plurality of transistors, the plurality of output signals configuring a differential signal and having signal levels that are different from each other; a plurality of timing adjustment circuits that each adjusts, on a basis of a timing setting signal, an input timing of corresponding one of the plurality of driver input signals to the driver circuit; and a control circuit that changes a set value of the timing setting signal for each of the plurality of timing adjustment circuits to a value corresponding to a plurality of transition states of possible signal levels of each of the plurality of output signals to be outputted from the driver circuit.

Abstract: To minimize failures in data writing in a semiconductor storage device in which a transistor is provided for each memory cell. A first transistor has a gate connected to a gate signal line and a source connected to a first source signal line. A second transistor has a gate connected to the gate signal line and a source connected to a second source signal line. A storage element is connected to drains of the first transistor and the second transistor. A gate signal line potential control unit controls a potential of the gate signal line such that the potential becomes a predetermined high potential that is higher than a predetermined reference potential in a case in which the storage element is caused to store data. A source signal line potential control unit causes one of the potentials of the first source signal line and the second signal line to drop such that the one of the potentials becomes lower than the predetermined reference potential, on a basis of the data.

Abstract: To minimize failures in data writing in a semiconductor storage device in which a transistor is provided for each memory cell. A first transistor has a gate connected to a gate signal line and a source connected to a first source signal line. A second transistor has a gate connected to the gate signal line and a source connected to a second source signal line. A storage element is connected to drains of the first transistor and the second transistor. A gate signal line potential control unit controls a potential of the gate signal line such that the potential becomes a predetermined high potential that is higher than a predetermined reference potential in a case in which the storage element is caused to store data. A source signal line potential control unit causes one of the potentials of the first source signal line and the second signal line to drop such that the one of the potentials becomes lower than the predetermined reference potential, on a basis of the data.

Abstract: A circuit includes a first driver, a second driver, a first capacitance, and a second capacitance. The first driver is configured to receive power supply from a first power source domain. The second driver is configured to receive power supply from a second power source domain that is different from the first power source domain. The first capacitance is connected to an output node of the first driver. The second capacitance is disposed between an output node of the second driver and the output node of the first driver.

Abstract: The present invention provides an image display device that includes projection lens (150) configured to project an image to a projection surface, and openable/closable lens cover (161) for covering the front of projection lens (150). The image display device includes focus adjustment control unit (320) that adjusts the focus of projection lens (150), and open/close detection unit (160) that detects the opened/closed state of lens cover (160) to notify focus adjustment control unit (320) of the result. Focus adjustment control unit (320) stops the focus adjustment when it is notified of the closing of lens cover (161) by open/close detection unit (160).

Abstract: A socket (1) includes a body (1a) and a cover (3). Body (1a) has a base (2) having a horizontally movable slide (4) thereon on which a BGA package can be mounted and a plurality of contact members (6) arranged on base (2) corresponding to a pattern of solder balls of the BGA package. Each of contact members (6) has a pair of spring arms (6a, 6b) which can be opened and closed in response to movement of slide (4). In one embodiment, a cover (3) is vertically movable relative to body (1a). The cover (3) has motion transfer portions (31) having a wedge shape which are engageable with tapered force receiving portions (43) of slide(4). As cover (3) is pushed down, engagement surfaces (31) of motion transfer portions (30) engage force receiving surfaces (43) of slide (4) and slide (4) moves so that arms (6a, 6b) of contact members (6) are opened. In another embodiment, the motion transfer parts (31) are provided on a head (11) which has an air suction holder for a BGA package.