Abstract: A processing system has a processing section for continuously processing a member to be processed; an inspection section for inspecting a processed state of the member processed by the processing section; a processed state determination section for determining whether the processed state is defective/nondefective, on the basis of a result of inspection performed by the inspection section; a continuity determination section for determining whether or not a defective determination is continuously made when the processed state is determined to be defective by the processed state determination section; and a processing control section for controlling processing so as to stop processing of the member continuously performed by the processing section when the continuity determination section determines that the defective determination is continuously made.

Abstract: A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.

Abstract: A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.