Patents by Inventor Yasuhiro Sambonsugi

Yasuhiro Sambonsugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method
    Patent number: 8088666
    Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasuhiro Sambonsugi, Hikaru Kokura
  • Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method
    Publication number: 20080311721
    Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.
    Type: Application
    Filed: September 17, 2007
    Publication date: December 18, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhiro Sambonsugi, Hikaru Kokura
  • Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
    Patent number: 7285449
    Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Sambonsugi, Hikaru Kokura
  • Semiconductor device using junction leak current
    Patent number: 6690071
    Abstract: A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second impurity diffusion regions of a second conductivity type on both sides of the gate electrode. A high leak current structure is formed which makes a leak current density when a reverse bias voltage is applied across the first impurity diffusion region and first well become higher than a leak current density when the same reverse bias voltage is applied across the second impurity diffusion region and first well.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: February 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Sambonsugi, Hiroyuki Ohta, Shinji Sugatani, Yoichi Morriyama
  • Semiconductor device using junction leak current and its manufacture method
    Publication number: 20030102516
    Abstract: A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second impurity diffusion regions of a second conductivity type on both sides of the gate electrode. A high leak current structure is formed which makes a leak current density when a reverse bias voltage is applied across the first impurity diffusion region and first well become higher than a leak current density when the same reverse bias voltage is applied across the second impurity diffusion region and first well.
    Type: Application
    Filed: November 13, 2002
    Publication date: June 5, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhiro Sambonsugi, Hiroyuki Ohta, Shinji Sugatani, Yoichi Momiyama
  • Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method
    Publication number: 20030098486
    Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 29, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yasuhiro Sambonsugi, Hikaru Kokura