Abstract: A static key interface circuit has an input terminal coupled to N key switches, where N is an integer greater than one. The N key switches are biased at different potentials, which are supplied to the input terminal when the key switches are closed. A multilevel detector in the key interface circuit detects the potential of the input terminal and generates corresponding result data. A dynamic key interface circuit has an input terminal coupled to P rows of N key switches each and scans the P rows in turn, using a similar multilevel detector. The multilevel detector increases the number of key switches connectable to a single input terminal by a factor of N.

Abstract: A drive voltage generating circuit outputs drive signals having voltage levels which is controlled by a second control signal is disclosed. A drive voltage generating circuit according to the present invention comprises drive output terminals for outputting drive signals having voltage levels, a bias circuit having a first voltage terminal to be applied to a first voltage and a second voltage terminal to be applied to a second voltage. The bias circuit produces voltage signals having the drive voltage levels. A drive voltage generating circuit according to the present invention further comprises a switching circuit having input terminals coupled to the bias circuit, output terminals coupled to the drive output terminals and a control terminal receiving a first control signal, a bias potential control circuit coupled between the second voltage terminal and a third voltage terminal to be applied to a third voltage.

Abstract: A method for reading data for a semiconductor memory device including steps of selecting a plurality of memory locations on which data are stored by word-lines and bit-lines, and reading the data from the bit-lines is provided, which comprises the steps of precharging the word-line by activating the first precharge signal; precharging the bit-line by activating a second precharge signal after a lapse of predetermined time since the first precharge signal has been activated; selecting a predetermined memory location in response to address signals; and reading data stored on the memory location from the bit-line by inactivating the first and second precharge signals.

Abstract: A flash analog-to-digital converter has CMOS comparators that compare an analog input signal with internal reference voltages and produce internal output signals. Each comparison is performed according to the threshold voltage of an inverter. A threshold control circuit in each comparator adjusts this threshold voltage according to the internal output signal, thereby providing hysteresis. A logic circuit receives the internal output signals from all the comparators and generates a digital output signal. The hysteresis of the comparators keeps the digital output signal from oscillating between adjacent values when the analog input signal is near one of the internal reference voltages.

Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the

Abstract: A level shifting circuit according to the present invention has first and second voltage terminals, first and second input terminals, an output terminal, a level converter circuit and an output circuit. The level converter includes first, second and third nodes, first, second, third and fourth transistors and an resistive element. The first transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the first node and a control electrode connected to the first input terminal. The second transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the second node and a control electrode connected to the second input terminal. The third transistor has a first electrode connected to the second voltage level, a second electrode connected to the first node and a control electrode connected to the second node. The resistive element connected between the second and third nodes.

Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the

Abstract: A first active element has its first terminal coupled to a first power-supply terminal, its second terminal coupled through a resistor to a second power-supply terminal, and its third terminal coupled to the second power-supply terminal, or to a control signal input terminal that is normally at the same potential as the second power-supply terminal. A second active element has its first terminal coupled to the second power-supply terminal, its second terminal coupled through a resistor to the first power-supply terminal, and its third terminal coupled to the second terminal of the first active element. A reset signal is taken from the second terminal of the second active element. The control signal can be used to prevent current flow during static current measurements.

Abstract: Disclosed herein is an LCD driver circuit comprising a plurality of cascade-connected LCD drivers. The LCD driver circuit can be activated to make a latch pulse signal input thereto active on the trailing edge thereof and operated even if a corresponding clock pulse signal is input in confronting relationship during a period in which the latch pulse signal is being input. Each of the LCD drivers has a latch pulse control circuit for selecting either one of a first latch pulse signal and a second latch pulse signal generated corresponding to the first latch pulse signal in accordance with an enable signal input at the time the LCD drivers are cascaded, thereby controlling an enable latch circuit and a shift register.

Abstract: A drive device with a data latch circuit which is formed of a plurality of latches, which successively latch serial drive data and output them in parallel, and a shift register having a plurality of first flip-flops which provide, responsive to clock pulses, latch signals for causing the latch to latch the serial data in succession. In one aspect of the invention, the shift register also outputs an end signal when output of the latch signals is completed, and a gate circuit which blocks input of the serial data to the data latch circuit responsive to the end signal.

Abstract: A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.

Abstract: A multi-level selecting circuit has a selecting section provided in a semiconductor chip by a CMOS process for selecting one of a plurality of input levels at a time, input terminals provided on the semiconductor chip for feeding a plurality of levels to the selecting section, and an output terminal provided on the semiconductor chip for outputting one of the plurality of levels having been selected by the selecting section. The selecting section has a plurality of MOS transistors each being provided in the semiconductor chip and connected between respective one of the plurality of input terminals and the output terminal for feeding, when turned on by external control, the input level on the input terminal to the output terminal. Source connecting lines each is connected between respective one of the input terminals and the source electrode of respective one of the MOS transistors for feeding a voltage on the input terminal to the source electrode.

Abstract: A MOS current switching circuit comprises a first MOSFET, a second MOSFET, a first control circuit, a second control circuit, and an inverting amplifier. The inverting amplifier receives an output voltage of a current source to provide a feedback bias voltage to the first and second control circuit which are controlled by a control signal. The first and second control circuits are complementary operated to each other in response to the control signal to provide the feedback bias voltage to the gate electrode of the first or second MOSFET. The first or second MOSFET passes selectively a noiseless constant current from the current source toward the output terminal.

Abstract: A CMOS output circuit including CMOS inverters, is formed on a semiconductor substrate and N MOS switching transistors are provided. The output circuit is responsive to an external control signal for switching a plurality of reference voltages and delivering them as multiple-level drive signals. The CMOS output circuit furthermore includes PMOS switching circuits connected in parallel with each of a plurality of CMOS transfer gates, CMOS inverters, and N MOS switching transistors for preventing a latch-up phenomenon of the CMOS inverters from being produced. The PMOS switching circuits are on-off controlled by a control signal obtained by converting an amplitude level of an external control signal.

Abstract: The swallow counter includes a two modulus prescaler which selectively divides a frequency of an input pulse according to a signal level of a control signal for producing a frequency divided signal, a first programmable counter which starts counting in response to the frequency divided signal to produce a first code signal, a second programmable counter which starts counting in response to the first code signal for producing a second code signal, a first code detector for detecting a specific code signal of the first and second code signals to produce a first pulse signal, a third programmable counter which, in response to the frequency divided signal, starts to count for producing a third code signal, a second code detector for detecting a specific bit of the third code signal for producing a second pulse signal utilized as a reset signal of the first to third programmable counters, a flip-flop circuit for selectively outputting a reset or set signal in response to the first or second pulse signal, and a per

Abstract: The three state input circuit includes a P channel MOS FET and an N channel MOS FET which are supplied with an input signal at their drain electrodes, and a pair of flip-flop circuits connected to source electrodes of respective FETS and acting as a memory. Gate electrodes of the FETs are supplied with timing signals. The circuit operates to sequentially and periodically judge the input states in accordance with the timing signals, and then the stores results of such judgements and then outputs the stored results as 2 bit binary signals.