Patents by Inventor Yasuhiro Shinma
Yasuhiro Shinma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9368424Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.Type: GrantFiled: May 20, 2005Date of Patent: June 14, 2016Assignee: Cypress Semiconductor CorporationInventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
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Patent number: 9293441Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: October 4, 2011Date of Patent: March 22, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Patent number: 9142440Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.Type: GrantFiled: December 3, 2008Date of Patent: September 22, 2015Assignee: Cypess Semiconductor CorporationInventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
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Patent number: 8174107Abstract: The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage.Type: GrantFiled: December 17, 2008Date of Patent: May 8, 2012Assignee: Spansion LLCInventor: Yasuhiro Shinma
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Publication number: 20120025364Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: ApplicationFiled: October 4, 2011Publication date: February 2, 2012Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
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Patent number: 8030179Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: September 9, 2009Date of Patent: October 4, 2011Assignee: Spansion, LLCInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Patent number: 7851260Abstract: A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated.Type: GrantFiled: December 10, 2008Date of Patent: December 14, 2010Assignee: Spansion LLCInventors: Junji Tanaka, Kouichi Meguro, Yasuhiro Shinma
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Patent number: 7846771Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.Type: GrantFiled: July 1, 2008Date of Patent: December 7, 2010Assignee: Spansion LLCInventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
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Patent number: 7696616Abstract: A stacked type semiconductor device includes semiconductor devices, interposers by which the semiconductor devices are stacked, the interposers having electrodes provided on sides thereof, and a connection substrate connecting the electrodes together. The electrodes provided on the sides of the interposers may be connected to the connection substrate by one of an electrically conductive adhesive or an anisotropically conductive film.Type: GrantFiled: January 25, 2006Date of Patent: April 13, 2010Assignee: Spansion LLCInventors: Yasuhiro Shinma, Masanori Onodera, Kouichi Meguro, Koji Taya, Junji Tanaka, Junichi Kasai
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Patent number: 7642637Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.Type: GrantFiled: August 22, 2007Date of Patent: January 5, 2010Assignee: Spansion LLCInventors: Masanori Onodera, Junichi Kasai, Kouichi Meguro, Junji Tanaka, Yasuhiro Shinma, Koji Taya
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Publication number: 20090325346Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: ApplicationFiled: September 9, 2009Publication date: December 31, 2009Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
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Publication number: 20090315166Abstract: The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage.Type: ApplicationFiled: December 17, 2008Publication date: December 24, 2009Inventor: Yasuhiro Shinma
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Publication number: 20090311831Abstract: A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated.Type: ApplicationFiled: December 10, 2008Publication date: December 17, 2009Inventors: Junji Tanaka, Kouichi Meguro, Yasuhiro Shinma
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Patent number: 7622067Abstract: An apparatus for manufacturing a semiconductor device includes an upper mold (21), a lower mold (22), and a plate (30, 130, 230) that includes at least one cavity (31) that receives resin and defines an outer shape and a thickness of a resin sealing portion, and a gate (32) through which the resin is guided to the cavity (31), the plate (30) being interposed between the upper mold (21) and the lower mold (22). The plate (130) further includes a resin film (132) fixed by viscoelastic or adhesive bonding to a side of thin plates (131) towards a substrate on which electrodes are provided. The semiconductor device is provided which has no resin burrs that occur on a substrate in an end portion of the molded body. The plate (30, 130, 230) is formed by multiple thin plates (231, 232, 233) joined by welding or positioned by positioning pins (237, 238).Type: GrantFiled: May 26, 2006Date of Patent: November 24, 2009Assignee: Spansion LLCInventor: Yasuhiro Shinma
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Patent number: 7605457Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: December 7, 2006Date of Patent: October 20, 2009Assignee: Spansion LLCInventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
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Publication number: 20090093085Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.Type: ApplicationFiled: December 3, 2008Publication date: April 9, 2009Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
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Patent number: 7489029Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.Type: GrantFiled: August 30, 2005Date of Patent: February 10, 2009Assignee: Spansion LLCInventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
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Publication number: 20080274591Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.Type: ApplicationFiled: July 1, 2008Publication date: November 6, 2008Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
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Patent number: 7414305Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.Type: GrantFiled: January 27, 2006Date of Patent: August 19, 2008Assignee: Spansion LLCInventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
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Publication number: 20070290320Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.Type: ApplicationFiled: August 22, 2007Publication date: December 20, 2007Inventors: Masanori Onodera, Junichi Kasai, Kouichi Meguro, Junji Tanaka, Yasuhiro Shinma, Koji Taya