Patents by Inventor Yasuhiro Shinma

Yasuhiro Shinma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368424
    Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: June 14, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
  • Patent number: 9293441
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: March 22, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 9142440
    Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 22, 2015
    Assignee: Cypess Semiconductor Corporation
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Patent number: 8174107
    Abstract: The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: May 8, 2012
    Assignee: Spansion LLC
    Inventor: Yasuhiro Shinma
  • Publication number: 20120025364
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Application
    Filed: October 4, 2011
    Publication date: February 2, 2012
    Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
  • Patent number: 8030179
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Spansion, LLC
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 7851260
    Abstract: A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: December 14, 2010
    Assignee: Spansion LLC
    Inventors: Junji Tanaka, Kouichi Meguro, Yasuhiro Shinma
  • Patent number: 7846771
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: December 7, 2010
    Assignee: Spansion LLC
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Patent number: 7696616
    Abstract: A stacked type semiconductor device includes semiconductor devices, interposers by which the semiconductor devices are stacked, the interposers having electrodes provided on sides thereof, and a connection substrate connecting the electrodes together. The electrodes provided on the sides of the interposers may be connected to the connection substrate by one of an electrically conductive adhesive or an anisotropically conductive film.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: April 13, 2010
    Assignee: Spansion LLC
    Inventors: Yasuhiro Shinma, Masanori Onodera, Kouichi Meguro, Koji Taya, Junji Tanaka, Junichi Kasai
  • Patent number: 7642637
    Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 5, 2010
    Assignee: Spansion LLC
    Inventors: Masanori Onodera, Junichi Kasai, Kouichi Meguro, Junji Tanaka, Yasuhiro Shinma, Koji Taya
  • Publication number: 20090325346
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Application
    Filed: September 9, 2009
    Publication date: December 31, 2009
    Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
  • Publication number: 20090315166
    Abstract: The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage.
    Type: Application
    Filed: December 17, 2008
    Publication date: December 24, 2009
    Inventor: Yasuhiro Shinma
  • Publication number: 20090311831
    Abstract: A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated.
    Type: Application
    Filed: December 10, 2008
    Publication date: December 17, 2009
    Inventors: Junji Tanaka, Kouichi Meguro, Yasuhiro Shinma
  • Patent number: 7622067
    Abstract: An apparatus for manufacturing a semiconductor device includes an upper mold (21), a lower mold (22), and a plate (30, 130, 230) that includes at least one cavity (31) that receives resin and defines an outer shape and a thickness of a resin sealing portion, and a gate (32) through which the resin is guided to the cavity (31), the plate (30) being interposed between the upper mold (21) and the lower mold (22). The plate (130) further includes a resin film (132) fixed by viscoelastic or adhesive bonding to a side of thin plates (131) towards a substrate on which electrodes are provided. The semiconductor device is provided which has no resin burrs that occur on a substrate in an end portion of the molded body. The plate (30, 130, 230) is formed by multiple thin plates (231, 232, 233) joined by welding or positioned by positioning pins (237, 238).
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: November 24, 2009
    Assignee: Spansion LLC
    Inventor: Yasuhiro Shinma
  • Patent number: 7605457
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: October 20, 2009
    Assignee: Spansion LLC
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Publication number: 20090093085
    Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.
    Type: Application
    Filed: December 3, 2008
    Publication date: April 9, 2009
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Patent number: 7489029
    Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: February 10, 2009
    Assignee: Spansion LLC
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Publication number: 20080274591
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Patent number: 7414305
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 19, 2008
    Assignee: Spansion LLC
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Publication number: 20070290320
    Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 20, 2007
    Inventors: Masanori Onodera, Junichi Kasai, Kouichi Meguro, Junji Tanaka, Yasuhiro Shinma, Koji Taya