Patents by Inventor Yasuhiro SHINOZUKA
Yasuhiro SHINOZUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085177Abstract: A photodetection device according to the present disclosure includes: a light-receiving section including a light-receiving element, a first switch, a second switch, and a signal generator, the first switch that couples the light-receiving element to a first node by being turned on, the second switch that applies a predetermined voltage to the first node by being turned on, and the signal generator that generates a pulse signal on the basis of a voltage at the first node; a controller that controls operations of the first switch and the second switch; a detector that detects a timing at which the pulse signal is changed, on the basis of the pulse signal; and an output section that outputs a detection signal corresponding to a detection result by the detector when the second switch is turned on.Type: ApplicationFiled: January 11, 2022Publication date: March 14, 2024Inventors: Ryutaro Homma, Yasuhiro Shinozuka
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Publication number: 20230132196Abstract: [Problem] To provide a light receiving apparatus, a light receiving circuit, and a distance measurement apparatus which can detect a photon with high accuracy, irrespective of illuminance in the environment. [Solution] A light receiving apparatus according to the present disclosure includes a first light receiving circuit configured such that it is possible to switch a recharge method for a light receiving element, and a control circuit configured to control the recharge method for the first light receiving circuit on the basis of a signal outputted by the first light receiving circuit in a reaction with a photon.Type: ApplicationFiled: October 13, 2020Publication date: April 27, 2023Inventors: Kumiko Mahara, Osamu Ozawa, Tomohiro Matsukawa, Yasuhiro Shinozuka
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Publication number: 20230048083Abstract: Provided are a light receiving device, a light receiving circuit, and a distance measuring device capable of minimizing dead time. A light receiving device according to the present disclosure may include: a light receiving circuit including a light receiving element; a power supply circuit configured to supply a power supply potential to the light receiving circuit; and a control circuit configured to control the power supply potential supplied by the power supply circuit on the basis of a signal output from the light receiving circuit in a reaction with a photon.Type: ApplicationFiled: December 23, 2020Publication date: February 16, 2023Inventors: KUMIKO MAHARA, OSAMU OZAWA, TOMOHIRO MATSUKAWA, YASUHIRO SHINOZUKA, KEITAROU AMAGAWA
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Patent number: 11543497Abstract: [Problem] The present disclosure proposes a technology that makes it possible to further reduce the influence of an error arising from a resolution of processing relating to measurement of the distance.Type: GrantFiled: September 12, 2018Date of Patent: January 3, 2023Assignee: Sony Semiconductor Solutions CorporationInventor: Yasuhiro Shinozuka
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Publication number: 20220075033Abstract: A light reception device according to an embodiment includes: a light receiving element (10001 to 1000n) in which a current flows according to an incident photon in a state where a predetermined voltage is applied and that returns to the state by a recharge current; a generation unit (1100a) that generates a reference current; and a copying unit (10011 to 1001n) that copies the reference current generated by the generation unit to generate a copy reference current. A recharge current based on the copy reference current is supplied to the light receiving element.Type: ApplicationFiled: January 7, 2020Publication date: March 10, 2022Inventor: Yasuhiro Shinozuka
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Publication number: 20210041540Abstract: A light receiving device of the present disclosure includes: a pixel array unit having a plurality of pixels 501 to 504 each including a light receiving unit 501 to 504 that generates a signal according to reception of photons; a first switch unit that 611 to 614 recharges the light receiving unit 501 to 504; and a recharge control unit 64 that controls the first switch unit 611 to 614 according to output of the light receiving unit 501 to 504, and the recharge control unit 64 is shared among the plurality of pixels 501 to 504. By this sharing of the recharge control unit 64, since the circuit area of the circuit unit 60 per pixel can be reduced, the aperture ratio can be increased while miniaturizing the pixel 50. Preferably, the recharge control unit 64 includes a four-input OR circuit 641 and a recharge signal generation circuit 642. The OR circuit 641 obtains the OR of the logic signals retrieved from each cathode electrode of the SPAD sensors 501 to 504 supplied through the comparators 631 to 634.Type: ApplicationFiled: March 6, 2019Publication date: February 11, 2021Applicant: Sony Semiconductor Solutions CorporationInventors: Yasuhiro Shinozuka, Hayato Kamizuru
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Publication number: 20190383917Abstract: [Problem] The present disclosure proposes a technology that makes it possible to further reduce the influence of an error arising from a resolution of processing relating to measurement of the distance.Type: ApplicationFiled: September 12, 2018Publication date: December 19, 2019Applicant: Sony Semiconductor Solutions CorporationInventor: Yasuhiro Shinozuka
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Patent number: 10473769Abstract: According to an embodiment, a distance measuring apparatus includes an irradiator that emits an irradiation wave to a measuring target, a first detector that directly detects the irradiation wave, a second detector that detects a reflection wave, a simulation signal generator that generates a simulation signal, a first meter that measures a first time and an emission time of the irradiation wave, a second meter that measures a second time and an incidence time of the reflection wave, a first subtractor that subtracts the emission time from the incidence time to obtain a measurement time period, and that subtracts the first time from the second time to obtain an error time period and a second subtractor that subtracts the error time period from the measurement time period to obtain an offset measurement time period.Type: GrantFiled: August 30, 2017Date of Patent: November 12, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shinozuka, Akihide Sai
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Patent number: 10422866Abstract: According to an embodiment, a distance measuring apparatus includes an irradiator that emits an irradiation wave to a measuring target, a first detector that directly detects the irradiation wave, a second detector that detects a reflection wave, a simulation signal generator that generates a simulation signal, a first meter that measures a first time and an emission time of the irradiation wave, a second meter that measures a second time and an incidence time of the reflection wave, a first subtractor that subtracts the emission time from the incidence time to obtain a measurement time period, and that subtracts the first time from the second time to obtain an error time period and a second subtractor that subtracts the error time period from the measurement time period to obtain an offset measurement time period.Type: GrantFiled: August 30, 2017Date of Patent: September 24, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shinozuka, Akihide Sai
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Publication number: 20180259627Abstract: According to an embodiment, a distance measuring apparatus includes an irradiator that emits an irradiation wave to a measuring target, a first detector that directly detects the irradiation wave, a second detector that detects a reflection wave, a simulation signal generator that generates a simulation signal, a first meter that measures a first time and an emission time of the irradiation wave, a second meter that measures a second time and an incidence time of the reflection wave, a first subtractor that subtracts the emission time from the incidence time to obtain a measurement time period, and that subtracts the first time from the second time to obtain an error time period and a second subtractor that subtracts the error time period from the measurement time period to obtain an offset measurement time period.Type: ApplicationFiled: August 30, 2017Publication date: September 13, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHINOZUKA, Akihide SAI
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Patent number: 9912898Abstract: According to an embodiment, an amplifier which amplifies a first signal to output a second signal includes the following elements. The comparator compares the first signal with a third signal to output a fourth signal. The delay circuit delays a fifth signal by a delay time to generate a sixth signal. The first capacitor is connected between a voltage source and a first node that provides the third signal. The second capacitor is connected between the first node and a second node that provides the second signal. The first switch is connected between the second node and a constant current source, and is controlled by the fourth signal and the fifth signal. The second switch is connected between the first node and the second node, and is controlled by the fifth signal and the sixth signal.Type: GrantFiled: September 3, 2016Date of Patent: March 6, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shinozuka, Masanori Furuta, Kei Shiraishi
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Publication number: 20170070695Abstract: According to an embodiment, an amplifier which amplifies a first signal to output a second signal includes the following elements. The comparator compares the first signal with a third signal to output a fourth signal. The delay circuit delays a fifth signal by a delay time to generate a sixth signal. The first capacitor is connected between a voltage source and a first node that provides the third signal. The second capacitor is connected between the first node and a second node that provides the second signal. The first switch is connected between the second node and a constant current source, and is controlled by the fourth signal and the fifth signal. The second switch is connected between the first node and the second node, and is controlled by the fifth signal and the sixth signal.Type: ApplicationFiled: September 3, 2016Publication date: March 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHINOZUKA, Masanori FURUTA, Kei SHIRAISHI
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Patent number: 9312873Abstract: An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.Type: GrantFiled: January 5, 2015Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanori Furuta, Kei Shiraishi, Yasuhiro Shinozuka
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Publication number: 20150194973Abstract: An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.Type: ApplicationFiled: January 5, 2015Publication date: July 9, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Masanori Furuta, Kei Shiraishi, Yasuhiro Shinozuka
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Publication number: 20150162929Abstract: An analog-to-digital converter has a comparator to compare, within a predetermined period, an input signal with a ramp signal or with a triangle wave signal, a first counter to count up or down in accordance with a logic of a signal that indicates a comparison result of the comparator within the predetermined period, a count value storage to sequentially store count values of the first counter whenever the logic of the signal that indicates a comparison result of the comparator changes within the predetermined period, a second counter to count the number of times the logic of the signal that indicates a comparison result of the comparator changes, and an arithmetic module to output a value obtained by adding up the count values stored in the count value storage and dividing the added-up value by a count value of the second counter.Type: ApplicationFiled: December 5, 2014Publication date: June 11, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHINOZUKA, Masanori FURUTA, Kei SHIRAISHI