Patents by Inventor Yasuhiro Soeda
Yasuhiro Soeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12246536Abstract: Provided is a technique that enables voltages to be applied, with high precision, to an electrode layer for inhibition and removal of koge while suppressing increase in the size a substrate. A liquid ejection head substrate includes: electrothermal conversion elements that apply heat to a liquid; an upper electrode part in which a plurality of upper electrodes that protect the electrothermal conversion elements are formed at positions where the upper electrodes come into contact with the liquid; a counter electrode part which is provided to correspond to the upper electrode part and in which a plurality of counter electrodes are formed to be electrically connectable to the upper electrodes via the liquid; and a generation unit that generates a voltage to be applied to at least one of the upper electrode part and the counter electrode part.Type: GrantFiled: November 30, 2021Date of Patent: March 11, 2025Assignee: CANON KABUSHIKI KAISHAInventors: Yasuo Fujii, Yasuhiro Soeda, Yosuke Miura
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Publication number: 20240419374Abstract: One embodiment of the present invention provides a method of sending print data, including: generating a first data part with a fixed data length; generating a second data part with a variable data length; and combining the first and second data parts in a predetermined order and sending the resulting print data. The first data part includes multiple information pieces. The second data part is capable of including multiple additional information pieces. A first information piece included in the first data part indicates presence or absence of each additional information piece in the second data part. The second information piece includes multiple pieces of synthesized data. In the sending, the multiple pieces of synthesized data are each subjected to bit division, and portions of the pieces of synthesized data subjected to the bit division which have a smaller bit length are continuously arranged in a single packet.Type: ApplicationFiled: June 5, 2024Publication date: December 19, 2024Inventors: YASUHIRO SOEDA, YOSUKE MIURA
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Publication number: 20240379179Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Suguru Taniguchi, Toshio Negishi, Yasuhiro Soeda
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Patent number: 12064965Abstract: According to the present invention, it is possible to provide an element substrate and a print head with which a decrease in yield and an increase in cost in a manufacturing process can be suppressed. For that purpose, a VH wiring line and a GNDH wiring line are provided in parallel in the same layer.Type: GrantFiled: September 1, 2022Date of Patent: August 20, 2024Assignee: CANON KABUSHIKI KAISHAInventors: Yosuke Miura, Yasuo Fujii, Yasuhiro Soeda
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Patent number: 12046309Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.Type: GrantFiled: March 10, 2022Date of Patent: July 23, 2024Assignee: CANON KABUSHIKI KAISHAInventors: Suguru Taniguchi, Toshio Negishi, Yasuhiro Soeda
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Patent number: 11981129Abstract: An element substrate comprises a plurality of stages of shift registers that inputs and holds a serial data signal; a latch circuit that latches the serial data held by the shift registers; a decoder circuit that inputs an output of the latch circuit and outputs a selection signal for selecting a block of the print elements or the memory elements; and a mask circuit that masks the output of the selection signal for selecting the block of the memory elements from the decoder circuit in accordance with an input bit data signal. The block of the print elements or the memory elements includes a plurality of print elements or memory elements in which one element is selected in each of the plurality of groups.Type: GrantFiled: March 10, 2022Date of Patent: May 14, 2024Assignee: CANON KABUSHIKI KAISHAInventors: Soichiro Nagamochi, Toshio Negishi, Yasuhiro Soeda
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Patent number: 11975536Abstract: An element substrate including a liquid discharge element, comprising a memory element capable of storing individual information of the element substrate by a write, the memory element being configured to change an impedance value by the write, a plurality of current supply elements capable of supplying a current to the memory element, and a determination unit configured to determine presence/absence of the write based on a voltage generated in the memory element by the current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit and each supply the current in an amount according to a size ratio to the memory element.Type: GrantFiled: February 11, 2022Date of Patent: May 7, 2024Assignee: Canon Kabushiki KaishaInventors: Toshio Negishi, Yasuhiro Soeda
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Patent number: 11837301Abstract: A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.Type: GrantFiled: March 3, 2022Date of Patent: December 5, 2023Assignee: Canon Kabushiki KaishaInventors: Masashi Fukuda, Toshio Negishi, Yasuhiro Soeda
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Publication number: 20230074434Abstract: According to the present invention, it is possible to provide an element substrate and a print head with which a decrease in yield and an increase in cost in a manufacturing process can be suppressed. For that purpose, a VH wiring line and a GNDH wiring line are provided in parallel in the same layer.Type: ApplicationFiled: September 1, 2022Publication date: March 9, 2023Inventors: Yosuke Miura, Yasuo Fujii, Yasuhiro Soeda
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Publication number: 20220288924Abstract: An element substrate comprises a plurality of stages of shift registers that inputs and holds a serial data signal; a latch circuit that latches the serial data held by the shift registers; a decoder circuit that inputs an output of the latch circuit and outputs a selection signal for selecting a block of the print elements or the memory elements; and a mask circuit that masks the output of the selection signal for selecting the block of the memory elements from the decoder circuit in accordance with an input bit data signal. The block of the print elements or the memory elements includes a plurality of print elements or memory elements in which one element is selected in each of the plurality of groups.Type: ApplicationFiled: March 10, 2022Publication date: September 15, 2022Inventors: Soichiro Nagamochi, Toshio Negishi, Yasuhiro Soeda
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Publication number: 20220293199Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.Type: ApplicationFiled: March 10, 2022Publication date: September 15, 2022Inventors: Suguru Taniguchi, Toshio Negishi, Yasuhiro Soeda
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Publication number: 20220293200Abstract: A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.Type: ApplicationFiled: March 3, 2022Publication date: September 15, 2022Inventors: Masashi Fukuda, Toshio Negishi, Yasuhiro Soeda
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Publication number: 20220293201Abstract: A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit.Type: ApplicationFiled: March 4, 2022Publication date: September 15, 2022Inventors: Sadayoshi Sakuma, Toshio Negishi, Yasuhiro Soeda
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Publication number: 20220266590Abstract: An element substrate including a liquid discharge element, comprising a memory element capable of storing individual information of the element substrate by a write, the memory element being configured to change an impedance value by the write, a plurality of current supply elements capable of supplying a current to the memory element, and a determination unit configured to determine presence/absence of the write based on a voltage generated in the memory element by the current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit and each supply the current in an amount according to a size ratio to the memory element.Type: ApplicationFiled: February 11, 2022Publication date: August 25, 2022Inventors: Toshio Negishi, Yasuhiro Soeda
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Publication number: 20220184952Abstract: Provided is a technique that enables voltages to be applied, with high precision, to an electrode layer for inhibition and removal of koge while suppressing increase in the size a substrate. A liquid ejection head substrate includes: electrothermal conversion elements that apply heat to a liquid; an upper electrode part in which a plurality of upper electrodes that protect the electrothermal conversion elements are formed at positions where the upper electrodes come into contact with the liquid; a counter electrode part which is provided to correspond to the upper electrode part and in which a plurality of counter electrodes are formed to be electrically connectable to the upper electrodes via the liquid; and a generation unit that generates a voltage to be applied to at least one of the upper electrode part and the counter electrode part.Type: ApplicationFiled: November 30, 2021Publication date: June 16, 2022Inventors: YASUO FUJII, YASUHIRO SOEDA, YOSUKE MIURA
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Patent number: 10126190Abstract: A capacitive force sensor 101 of the present invention includes a plurality of cells each including a lower electrode 104, a movable member that includes an upper electrode 107 and has flexibility, and a support 105b arranged to movably support the movable member and to form a gap 106 between the upper and the lower electrodes. The plural cells are grouped into elements each including one or more of the cells, and the one or more cells in a same element are electrically connected to each other.Type: GrantFiled: April 24, 2015Date of Patent: November 13, 2018Assignee: Canon Kabushiki KaishaInventors: Yasuhiro Soeda, Yasuhiro Shimada
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Publication number: 20170074734Abstract: A capacitive force sensor 101 of the present invention includes a plurality of cells each including a lower electrode 104, a movable member that includes an upper electrode 107 and has flexibility, and a support 105b arranged to movably support the movable member and to form a gap 106 between the upper and the lower electrodes. The plural cells are grouped into elements each including one or more of the cells, and the one or more cells in a same element are electrically connected to each other.Type: ApplicationFiled: April 24, 2015Publication date: March 16, 2017Inventors: Yasuhiro Soeda, Yasuhiro Shimada
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Patent number: 8754490Abstract: An element array comprises a plurality of elements having a first electrode and a second electrode with a gap therebetween; the first electrode is separated for each of the elements by grooves, an insulating connection substrate is bonded to the first electrode, and wirings are provided from the respective first electrodes through the connection substrate to the side opposite to the first electrodes.Type: GrantFiled: May 31, 2013Date of Patent: June 17, 2014Assignee: Canon Kabushiki KaishaInventors: Takahiro Ezaki, Chienliu Chang, Yasuhiro Soeda, Kenji Tamamori
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Patent number: 8665672Abstract: A process for producing a capacitive electromechanical conversion device by bonding together a substrate and a membrane member to form a cavity sealed between the substrate and the membrane member, the process for producing a capacitive electromechanical conversion device comprises the steps of: providing a gas release path penetrating from a bonded interface between the substrate and the membrane member to the outside, and forming the cavity by bonding the membrane member with the substrate with the gas release path provided; the gas release path being provided at a location where the path does not communicate with the cavity.Type: GrantFiled: June 4, 2009Date of Patent: March 4, 2014Assignee: Canon Kabushiki KaishaInventors: Yasuhiro Soeda, Takahiro Ezaki
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Publication number: 20130321039Abstract: A measuring device comprises a plurality of variable capacitors as sensor elements. The plurality of variable capacitors are provided with a drive circuit for each pair. The first electrodes of the two variable capacitors in each pair are electrically connected to each other. The drive circuit for each pair includes a bias supply for applying two AC bias voltages relatively 90° out of phase to the second electrodes respectively of the two variable capacitors to produce an output signal at the first electrodes connected to each other, a multiplier for multiplying the output signal by two AC signals relatively 90° out of phase to produce two multiplication signals, and an integrator for integrating the two multiplication signals for each cycle of the corresponding AC bias voltages to acquire two integration signals for the two variable capacitors.Type: ApplicationFiled: May 17, 2013Publication date: December 5, 2013Applicant: CANON KABUSHIKI KAISHAInventor: Yasuhiro Soeda