Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.

Abstract: Timers #0 through #3 are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an operating frequency for a CPU core corresponding to any of the timers #0 through #3 when the timer exceeds the prohibition period. It is determined whether it is necessary to change a power supply voltage supplied to CPU cores #0 through #3 when the OS #A or the OS #B determines necessity to change an operating frequency. When it is determined that a power supply voltage needs to be changed, a power supply voltage change portion 20 changes the power supply voltage supplied to the CPU cores #0 through #3. Therefore, it is possible to improve the processing efficiency without needing to acquire inter-OS lock.

Abstract: There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU#0 through VCPU#2 each operate different OS's. VCPU#0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU#0 regardless of an execution sequence stored in schedule register A. VCPU#0 reinitializes a bus where an error occurred.

Abstract: Timers #0 through #3 are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an operating frequency for a CPU core corresponding to any of the timers #0 through #3 when the timer exceeds the prohibition period. It is determined whether it is necessary to change a power supply voltage supplied to CPU cores #0 through #3 when the OS #A or the OS #B determines necessity to change an operating frequency. When it is determined that a power supply voltage needs to be changed, a power supply voltage change portion 20 changes the power supply voltage supplied to the CPU cores #0 through #3. Therefore, it is possible to improve the processing efficiency without needing to acquire inter-OS lock.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.

Abstract: A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.

Abstract: A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.