Abstract: A redundancy gateway system that can avoid short interruption of data communication caused by system switching in gateway units configured in a multiplex manner for a plurality of systems, and that can maintain the communication state prior to the system switching and avoid degradation of communication quality. A duplicate of a received packet is generated, thereby supplying the packet of the same content to a configuration of gateway units. For each packet, a common write pointer corresponding to identification information appended to the packet is generated. Each gateway unit writes the packet to its own jitter buffer in accordance with the common write pointer corresponding to each supplied packet, sequentially reads out the written packet from the jitter buffer, and generates a TDM signal. One of the gateway units is selectively switched and only the TDM signal generated by the one gateway unit is supplied to a TDM network.

Abstract: A redundancy gateway system that can avoid, to the maximum extent, short interruption of data communication caused by system switching in gateway units configured in a multiplex manner for a plurality of systems, and that can maintain the communication state prior to the system switching and avoid degradation of communication quality. A duplicate of a received packet is generated, thereby supplying the packet of the same content to a plurality of gateway units. For each packet, a common write pointer corresponding to identification information appended to the packet is generated. Each of the plurality of gateway units writes the packet to its own jitter buffer in accordance with the common write pointer corresponding to each supplied packet, sequentially reads out the written packet from the jitter buffer, and generates a TDM signal. One of the plurality of gateway units is selectively switched and only the TDM signal generated by the one gateway unit is supplied to a TDM network.

Abstract: In a cell assembling device, an ATM cell assemblage decomposes input signals channel by channel and outputs channel-by-channel signals. At the same time, the cell assemblage generates a write control signal. Further, when one cell of data is written to a buffer, the cell assemblage generates a condition report signal for informing an arbitrating circuit of the channel of the cell. In response, the arbitrating circuit determines a channel to read out on the basis of the amounts of cell data stored in the buffer, and then outputs a read control signal meant for the above channel. On receiving the write control signal, the buffer writes the channel-by-channel signal therein. In response to the read control signal, the buffer outputs the signal of the channel designated by the signal and feeds it to a cell transmission circuit. The transmission circuit adds a cell header to the data output from the buffer to thereby form a cell to be sent.