Abstract: According to the present invention, a flavoring-loaded component for a tobacco product includes a component for a tobacco product and a flavoring composition that is loaded on the component and includes a flavoring and an emulsifier that has an HLB of 1-7.

Abstract: A semiconductor integrated circuit having an internal circuit group, which includes at least one internal circuit, includes a plurality of process monitoring circuits, each of which is disposed at a different location in the internal circuit group, each of the process monitoring circuits, which is operated in response to a power supply voltage, detecting monitoring data in the area where one of the process monitoring circuits is disposed, and a power supply voltage generating circuit generating the power supply voltage corresponding to the monitoring data, and supplying the power supply voltage to the internal circuit group.

Abstract: A semiconductor integrated circuit includes one or more voltage drop detection circuits located at one or more measurement points within the integrated circuit to detect drops in the power supply potential at those points. The voltage drop detection circuits output signals indicating whether the power supply potential is within tolerance, or whether the power supply potential has fallen and corrective action is required. Being located near the measurement points, the voltage drop detection circuits can measure the power supply potential without being disturbed by electrical noise elsewhere in the semiconductor integrated circuit. The signals output by the voltage detection circuits can be reliably brought to external terminals despite the presence of such noise, because the output signals are bi-level signals.

Abstract: A semiconductor integrated circuit having an internal circuit group, which includes at least one internal circuit, includes a plurality of process monitoring circuits, each of which is disposed at a different location in the internal circuit group, each of the process monitoring circuits, which is operated in response to a power supply voltage, detecting monitoring data in the area where one of the process monitoring circuits is disposed, and a power supply voltage generating circuit generating the power supply voltage corresponding to the monitoring data, and supplying the power supply voltage to the internal circuit group.

Abstract: A semiconductor integrated circuit includes one or more voltage drop detection circuits located at one or more measurement points within the integrated circuit to detect drops in the power supply potential at those points. The voltage drop detection circuits output signals indicating whether the power supply potential is within tolerance, or whether the power supply potential has fallen and corrective action is required. Being located near the measurement points, the voltage drop detection circuits can measure the power supply potential without being disturbed by electrical noise elsewhere in the semiconductor integrated circuit. The signals output by the voltage detection circuits can be reliably brought to external terminals despite the presence of such noise, because the output signals are bi-level signals.

Abstract: A temperature detection circuit is provided inside a chip which is the same in which a CPU is provided, and includes a temperature detection part having a PMOS transistor and an NMOS transistor connected in series between a power supply potential VDD and a grounding potential. A stray capacitance between a junction (live node) between the PMOS transistor and the NMOS transistor, and the grounding potential, is charged with a current differential between the off leak current of the PMOS transistor and the off leak current of the NMOS transistor, thereby changing the potential of the live node. When the changed potential reaches a level of a threshold value in a given period of time, it is decided that the temperature of the CPU reaches a set temperature.

Abstract: A temperature detection circuit is provided inside a chip which is the same as a CPU, and it comprises a temperature detection part comprised of a PMOS transistor and an NMOS transistor connected in series between a power supply potential VDD and a grounding potential, wherein a stray capacitance between a junction (live node) between the PMOS transistor and the NMOS transistor and the grounding potential is charged with a current differential between the off leak current of the PMOS transistor and the off leak current of the NMOS transistor, thereby changing the potential of the live node, and when the changed potential reaches a level of a threshold value in a given period of time, it is decided that the temperature of the CPU reaches a set temperature.

Abstract: Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a memory section of the semiconductor memory circuit and shorten the time necessary for its test.

Abstract: A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines.

Abstract: A semiconductor memory device includes a plurality of bit lines, a plurality of memory cells connected to the bit line. The semiconductor memory device also includes control circuits, a first control line and a second control line. The control circuit outputs a control signal. The first control line is formed by a first low resistance conductive layer and is connected to the control circuit to transfer the control signal. The first control signal extends to a first direction. A second control line is formed by a second low resistance conductive layer which is separated from the first conductive layer by an insulating layer. The second control line is connected to the control circuit to transfer the control signal and extends to a second direction which is substantially different from the first direction.