Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

Abstract: A boosting circuit includes a charge pump circuit; and a power supply circuit configured to supply a power supply voltage to the charge pump circuit. The power supply circuit includes an N-channel transistor connected with a power supply terminal of the charge pump circuit; and a current control circuit configured to control current flowing between the N-channel transistor and the charge pump circuit through the power supply terminal.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A boosting circuit includes a charge pump circuit; and a power supply circuit configured to supply a power supply voltage to the charge pump circuit. The power supply circuit includes an N-channel transistor connected with a power supply terminal of the charge pump circuit; and a current control circuit configured to control current flowing between the N-channel transistor and the charge pump circuit through the power supply terminal.

Abstract: A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage.

Abstract: A readout circuit has: a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through the memory cell transistor and a reference current flowing through a dummy cell transistor; and a voltage control circuit configured to apply a first voltage to a gate of the dummy cell transistor in a read operation. The memory cell transistor has a control gate and a floating gate. The voltage control circuit sets the first voltage such that a voltage between the gate and a source of the dummy cell transistor is lower than a voltage between the control gate and a source of the memory cell transistor.

Abstract: A readout circuit has: a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through the memory cell transistor and a reference current flowing through a dummy cell transistor; and a voltage control circuit configured to apply a first voltage to a gate of the dummy cell transistor in a read operation. The memory cell transistor has a control gate and a floating gate. The voltage control circuit sets the first voltage such that a voltage between the gate and a source of the dummy cell transistor is lower than a voltage between the control gate and a source of the memory cell transistor.

Abstract: A reference voltage generator circuit comprises a band gap circuit and a level correction regulator circuit. The band gap circuit generates output voltages REF 1, REF 2 having temperature dependence according to each of the write/erase mode and verify/read mode by setting the resistance values of resistors, and one of the output voltages is selected by a transfer gate and is regarded as REF. The level correction regulator circuit generates, based on the output REF, an output voltage OUT (reference voltage) on a level which is required for each mode. By virtue of the above construction, a level correction regulator circuit and one band gap circuit can constitute a reference voltage generator circuit for a nonvolatile memory which can realize temperature characteristics according to each mode while reducing the layout area.

Abstract: A reference voltage generator circuit comprises a band gap circuit and a level correction regulator circuit. The bard gap circuit generates output voltages REF 1, REF 2 having temperature dependence according to each of write/erase mode and verify/read mode by setting the resistance values of resistors, and one of the output voltages is selected by a transfer gate and is regarded as REF. The level correction regulator circuit generates, based on the output REF, an output voltage OUT (reference voltage) on a level which is required for each mode. By virtue of the above construction, a level correction regulator circuit and one band gap circuit can constitute a reference voltage generator circuit for a nonvolatile memory which can realize temperature characteristics according to each mode while reducing the layout area.

Abstract: A band-gap reference circuit generates and supplies a predetermined stable voltage (VREF). The band-gap reference circuit is comprised of three major circuits: a start-up circuit, which is comprised of a start-up transistor that is smaller than each of those in a band-gap circuit which generates a predetermined stable voltage and which outputs a start signal; a signal level converter, which converts said start signal to a second start signal that is supplied to said start-up transistor; and the band-gap circuit. The start-up transistor has a threshold voltage with its absolute value being smaller than each of those of the threshold voltages of transistors in said band-gap circuit. Moreover, the start-up transistor is (1/n) the channel length of said reference-voltage generation transistor and (1/n) the channel width of said reference-voltage generation transistor, where said n denotes a certain positive number larger than 1.

Abstract: A ROM includes a sense amplifier implemented by a current mirror circuit having a data line, a memory cell array, a plurality of digit lines and column selector for coupling the data line to one of the digit lines. The precharge circuit couples the data line to the ground during an initial stage of the precharge period to precharge the data line before the column selector couples the data line to the one of the digit lines, and also precharges the digit line through the data line after the column selector selects the digit line. A higher precharge operation can be achieved by the standby mode of the precharge circuit while precharging the data line.

Abstract: A non-volatile semiconductor memory includes a reference voltage generating circuit including a series circuit formed of a resistor and a diode, and a constant current circuit for supplying a constant current having a temperature dependency different from that of the diode, to the series circuit, so as to generate at one end of the series circuit a reference voltage having a temperature dependency equivalent to that of the threshold voltage of an erased memory cell. An erase verify voltage generating circuit generates on the basis of the reference voltage an erase verify voltage having a temperature dependency equivalent to that of the threshold voltage of the erased memory cell, and a read voltage generating circuit generates on the basis of the reference voltage a read voltage having a temperature dependency equivalent to that of the threshold voltage of the erased memory cell.